From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B88EA0527; Mon, 9 Nov 2020 14:44:54 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0CDE95B30; Mon, 9 Nov 2020 14:44:52 +0100 (CET) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by dpdk.org (Postfix) with ESMTP id B9C4F5AB8 for ; Mon, 9 Nov 2020 14:44:48 +0100 (CET) Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CVC0K2JhDzkhVB for ; Mon, 9 Nov 2020 21:44:33 +0800 (CST) Received: from [10.67.103.119] (10.67.103.119) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Mon, 9 Nov 2020 21:44:36 +0800 To: Ferruh Yigit CC: , References: <1604586194-29523-1-git-send-email-oulijun@huawei.com> <1604634716-43484-1-git-send-email-oulijun@huawei.com> <1604634716-43484-5-git-send-email-oulijun@huawei.com> From: oulijun Message-ID: <292d54bb-eb0e-438c-27ba-e53e3224809a@huawei.com> Date: Mon, 9 Nov 2020 21:44:36 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.103.119] X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH v2 4/5] net/hns3: check PCI config space writes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 在 2020/11/7 0:45, Ferruh Yigit 写道: > On 11/6/2020 3:51 AM, Lijun Ou wrote: >> Here adds a check for the return value when calling >> rte_pci_write_config. >> >> Coverity issue: 363714 >> Fixes: cea37e513329 ("net/hns3: fix FLR reset") >> Cc: stable@dpdk.org >> >> Signed-off-by: Lijun Ou >> --- >> V1->V2: >> - rte_pci_wirte_config -> rte_pci_write_config >> --- >> drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++--- >> 1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/hns3/hns3_ethdev_vf.c >> b/drivers/net/hns3/hns3_ethdev_vf.c >> index 2e9bfda..2f6d91b 100644 >> --- a/drivers/net/hns3/hns3_ethdev_vf.c >> +++ b/drivers/net/hns3/hns3_ethdev_vf.c >> @@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device >> *device, bool op) >> ret = rte_pci_read_config(device, &control, sizeof(control), >> (pos + PCI_MSIX_FLAGS)); >> if (ret < 0) { >> - PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", >> + PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x", > > Can you please drop this unrelated change from the patch? > Yes. I will fix it >> (pos + PCI_MSIX_FLAGS)); >> return -ENXIO; >> } >> @@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device >> *device, bool op) >> control |= PCI_MSIX_FLAGS_ENABLE; >> else >> control &= ~PCI_MSIX_FLAGS_ENABLE; >> - rte_pci_write_config(device, &control, sizeof(control), >> - (pos + PCI_MSIX_FLAGS)); >> + ret = rte_pci_write_config(device, &control, sizeof(control), >> + (pos + PCI_MSIX_FLAGS)); >> + if (ret < 0) { >> + PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", >> + (pos + PCI_MSIX_FLAGS)); >> + } >> return 0; >> } >> return -ENXIO; >> > > . >