From: Thomas Monjalon <thomas.monjalon@6wind.com>
To: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH] EAL:fix memory barrier implementation on IBM POWER
Date: Thu, 21 Jul 2016 16:24:23 +0200 [thread overview]
Message-ID: <2952292.tI9mo3Bcbg@xps13> (raw)
In-Reply-To: <1468549819-22764-1-git-send-email-chaozhu@linux.vnet.ibm.com>
2016-07-15 10:30, Chao Zhu:
> On weak memory order architecture like POWER, rte_smp_wmb/rte_smp_rmb
> need to use CPU instructions, not compiler barrier. This patch fixes
> this. Also, to improve performance on PPC64, use light weight sync
> instruction instead of sync instruction.
>
> Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Applied, thanks
prev parent reply other threads:[~2016-07-21 14:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-15 2:30 Chao Zhu
2016-07-21 14:24 ` Thomas Monjalon [this message]
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