From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 91CE2A0548; Tue, 22 Jun 2021 18:49:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BE2D40040; Tue, 22 Jun 2021 18:49:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 22A5F4003C for ; Tue, 22 Jun 2021 18:49:11 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15MGjMkx013066; Tue, 22 Jun 2021 09:49:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2hkGVyNBdmm2xUsUuUe2IvKDA7l0JryItnDO3NK0ZPw=; b=B5K1MZWILIrEAqJsbAmCNPzwcfEVSJ77EYCiZaAHluqmA2lfonHf+rKIfN8m1MBP3Nmp dpHulvfEEknpqQFATokRr1NhMlJJEXlttCbFzxSG4gP9aURUJHUZRalbJA2bBOOr3KeJ NquXR2LL1BS/MIMpw3Endl7/SCt5k85twgqPtjyf+ZfDesQ8vAUbwms8c4vbNFzspajE a732nmi2AaU6z+IQHjaWlHnMnaRCgzZ0GXCT2Hbqvm67v9gsr4wx3eT8lA6WhmfKAKI6 h1LbKU8BPMlW5rSZfm0fVy+AxkK+b+wiL9Wt+3noGnehIeEAfw1/622FWSpVedpCkBRt JA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 39b91haupy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 22 Jun 2021 09:49:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Jun 2021 09:49:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 22 Jun 2021 09:49:09 -0700 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 870105B6925; Tue, 22 Jun 2021 09:49:07 -0700 (PDT) From: Shijith Thotton To: CC: , , , , , , Date: Tue, 22 Jun 2021 22:18:08 +0530 Message-ID: <2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624379833.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: oZIXbKS_ulqrSEOWOL4fNr5negpIxwDR X-Proofpoint-GUID: oZIXbKS_ulqrSEOWOL4fNr5negpIxwDR X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-22_11:2021-06-22, 2021-06-22 signatures=0 Subject: [dpdk-dev] [PATCH 1/2] drivers: add octeontx crypto adapter framework X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Set crypto adapter event device slow-path call backs. Signed-off-by: Shijith Thotton --- drivers/crypto/octeontx/meson.build | 1 + drivers/crypto/octeontx/otx_cryptodev.c | 4 ++ drivers/crypto/octeontx/otx_cryptodev.h | 4 -- .../crypto/octeontx/otx_cryptodev_hw_access.h | 1 + drivers/event/octeontx/meson.build | 1 + drivers/event/octeontx/ssovf_evdev.c | 67 +++++++++++++++++++ 6 files changed, 74 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build index daef47a72f..37603c5c89 100644 --- a/drivers/crypto/octeontx/meson.build +++ b/drivers/crypto/octeontx/meson.build @@ -7,6 +7,7 @@ endif deps += ['bus_pci'] deps += ['common_cpt'] +deps += ['eventdev'] sources = files( 'otx_cryptodev.c', diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c index ba73c2f939..7207909abb 100644 --- a/drivers/crypto/octeontx/otx_cryptodev.c +++ b/drivers/crypto/octeontx/otx_cryptodev.c @@ -14,6 +14,10 @@ #include "cpt_pmd_logs.h" +/* Device ID */ +#define PCI_VENDOR_ID_CAVIUM 0x177d +#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041 + uint8_t otx_cryptodev_driver_id; static struct rte_pci_id pci_id_cpt_table[] = { diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h index b66ef4a8f7..5d8607eafb 100644 --- a/drivers/crypto/octeontx/otx_cryptodev.h +++ b/drivers/crypto/octeontx/otx_cryptodev.h @@ -8,10 +8,6 @@ /* Cavium OCTEON TX crypto PMD device name */ #define CRYPTODEV_NAME_OCTEONTX_PMD crypto_octeontx -/* Device ID */ -#define PCI_VENDOR_ID_CAVIUM 0x177d -#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041 - #define CPT_LOGTYPE otx_cpt_logtype extern int otx_cpt_logtype; diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h index 0ec258157a..f7b1e93402 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h @@ -45,6 +45,7 @@ struct cpt_instance { struct rte_mempool *sess_mp; struct rte_mempool *sess_mp_priv; struct cpt_qp_meta_info meta_info; + uint8_t ca_enabled; }; struct command_chunk { diff --git a/drivers/event/octeontx/meson.build b/drivers/event/octeontx/meson.build index 3cb140b4de..0d9eec3f2e 100644 --- a/drivers/event/octeontx/meson.build +++ b/drivers/event/octeontx/meson.build @@ -12,3 +12,4 @@ sources = files( ) deps += ['common_octeontx', 'mempool_octeontx', 'bus_vdev', 'net_octeontx'] +deps += ['crypto_octeontx'] diff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c index d8b359801a..25bf207db6 100644 --- a/drivers/event/octeontx/ssovf_evdev.c +++ b/drivers/event/octeontx/ssovf_evdev.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include "ssovf_evdev.h" #include "timvf_evdev.h" +#include "otx_cryptodev_hw_access.h" static uint8_t timvf_enable_stats; @@ -725,6 +727,67 @@ ssovf_timvf_caps_get(const struct rte_eventdev *dev, uint64_t flags, timvf_enable_stats); } +static int +ssovf_crypto_adapter_caps_get(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, uint32_t *caps) +{ + RTE_SET_USED(dev); + RTE_SET_USED(cdev); + + *caps = 0; + + return 0; +} + +static int +ssovf_crypto_adapter_qp_add(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, + int32_t queue_pair_id, + const struct rte_event *event) +{ + struct cpt_instance *qp; + uint8_t qp_id; + + RTE_SET_USED(event); + + if (queue_pair_id == -1) { + for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) { + qp = cdev->data->queue_pairs[qp_id]; + qp->ca_enabled = 1; + } + } else { + qp = cdev->data->queue_pairs[queue_pair_id]; + qp->ca_enabled = 1; + } + + ssovf_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); + + return 0; +} + +static int +ssovf_crypto_adapter_qp_del(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, + int32_t queue_pair_id) +{ + struct cpt_instance *qp; + uint8_t qp_id; + + RTE_SET_USED(dev); + + if (queue_pair_id == -1) { + for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) { + qp = cdev->data->queue_pairs[qp_id]; + qp->ca_enabled = 0; + } + } else { + qp = cdev->data->queue_pairs[queue_pair_id]; + qp->ca_enabled = 0; + } + + return 0; +} + /* Initialize and register event driver with DPDK Application */ static struct rte_eventdev_ops ssovf_ops = { .dev_infos_get = ssovf_info_get, @@ -755,6 +818,10 @@ static struct rte_eventdev_ops ssovf_ops = { .timer_adapter_caps_get = ssovf_timvf_caps_get, + .crypto_adapter_caps_get = ssovf_crypto_adapter_caps_get, + .crypto_adapter_queue_pair_add = ssovf_crypto_adapter_qp_add, + .crypto_adapter_queue_pair_del = ssovf_crypto_adapter_qp_del, + .dev_selftest = test_eventdev_octeontx, .dump = ssovf_dump, -- 2.25.1