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From: Shijith Thotton <sthotton@marvell.com>
To: <dev@dpdk.org>
CC: Shijith Thotton <sthotton@marvell.com>, <pbhagavatula@marvell.com>,
<anoobj@marvell.com>, <jerinj@marvell.com>,
<abhinandan.gujjar@intel.com>, <adwivedi@marvell.com>, <gakhil@marvell.com>
Date: Thu, 24 Jun 2021 02:23:49 +0530
Message-ID: <2bd2c4be2295105b81843d31c1bcb4dab7e1aff7.1624481225.git.sthotton@marvell.com>
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Subject: [dpdk-dev] [PATCH v2 1/2] drivers: add octeontx crypto adapter
framework
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Set crypto adapter event device slow-path call backs.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
---
drivers/crypto/octeontx/meson.build | 1 +
drivers/crypto/octeontx/otx_cryptodev.c | 4 ++
drivers/crypto/octeontx/otx_cryptodev.h | 4 --
.../crypto/octeontx/otx_cryptodev_hw_access.h | 1 +
drivers/event/octeontx/meson.build | 1 +
drivers/event/octeontx/ssovf_evdev.c | 67 +++++++++++++++++++
6 files changed, 74 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build
index daef47a72f..37603c5c89 100644
--- a/drivers/crypto/octeontx/meson.build
+++ b/drivers/crypto/octeontx/meson.build
@@ -7,6 +7,7 @@ endif
deps += ['bus_pci']
deps += ['common_cpt']
+deps += ['eventdev']
sources = files(
'otx_cryptodev.c',
diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c
index ba73c2f939..7207909abb 100644
--- a/drivers/crypto/octeontx/otx_cryptodev.c
+++ b/drivers/crypto/octeontx/otx_cryptodev.c
@@ -14,6 +14,10 @@
#include "cpt_pmd_logs.h"
+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM 0x177d
+#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041
+
uint8_t otx_cryptodev_driver_id;
static struct rte_pci_id pci_id_cpt_table[] = {
diff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h
index b66ef4a8f7..5d8607eafb 100644
--- a/drivers/crypto/octeontx/otx_cryptodev.h
+++ b/drivers/crypto/octeontx/otx_cryptodev.h
@@ -8,10 +8,6 @@
/* Cavium OCTEON TX crypto PMD device name */
#define CRYPTODEV_NAME_OCTEONTX_PMD crypto_octeontx
-/* Device ID */
-#define PCI_VENDOR_ID_CAVIUM 0x177d
-#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041
-
#define CPT_LOGTYPE otx_cpt_logtype
extern int otx_cpt_logtype;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
index 0ec258157a..f7b1e93402 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h
@@ -45,6 +45,7 @@ struct cpt_instance {
struct rte_mempool *sess_mp;
struct rte_mempool *sess_mp_priv;
struct cpt_qp_meta_info meta_info;
+ uint8_t ca_enabled;
};
struct command_chunk {
diff --git a/drivers/event/octeontx/meson.build b/drivers/event/octeontx/meson.build
index 3cb140b4de..0d9eec3f2e 100644
--- a/drivers/event/octeontx/meson.build
+++ b/drivers/event/octeontx/meson.build
@@ -12,3 +12,4 @@ sources = files(
)
deps += ['common_octeontx', 'mempool_octeontx', 'bus_vdev', 'net_octeontx']
+deps += ['crypto_octeontx']
diff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c
index d8b359801a..25bf207db6 100644
--- a/drivers/event/octeontx/ssovf_evdev.c
+++ b/drivers/event/octeontx/ssovf_evdev.c
@@ -5,6 +5,7 @@
#include <inttypes.h>
#include <rte_common.h>
+#include <rte_cryptodev.h>
#include <rte_debug.h>
#include <rte_dev.h>
#include <rte_eal.h>
@@ -19,6 +20,7 @@
#include "ssovf_evdev.h"
#include "timvf_evdev.h"
+#include "otx_cryptodev_hw_access.h"
static uint8_t timvf_enable_stats;
@@ -725,6 +727,67 @@ ssovf_timvf_caps_get(const struct rte_eventdev *dev, uint64_t flags,
timvf_enable_stats);
}
+static int
+ssovf_crypto_adapter_caps_get(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev, uint32_t *caps)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(cdev);
+
+ *caps = 0;
+
+ return 0;
+}
+
+static int
+ssovf_crypto_adapter_qp_add(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev,
+ int32_t queue_pair_id,
+ const struct rte_event *event)
+{
+ struct cpt_instance *qp;
+ uint8_t qp_id;
+
+ RTE_SET_USED(event);
+
+ if (queue_pair_id == -1) {
+ for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {
+ qp = cdev->data->queue_pairs[qp_id];
+ qp->ca_enabled = 1;
+ }
+ } else {
+ qp = cdev->data->queue_pairs[queue_pair_id];
+ qp->ca_enabled = 1;
+ }
+
+ ssovf_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);
+
+ return 0;
+}
+
+static int
+ssovf_crypto_adapter_qp_del(const struct rte_eventdev *dev,
+ const struct rte_cryptodev *cdev,
+ int32_t queue_pair_id)
+{
+ struct cpt_instance *qp;
+ uint8_t qp_id;
+
+ RTE_SET_USED(dev);
+
+ if (queue_pair_id == -1) {
+ for (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {
+ qp = cdev->data->queue_pairs[qp_id];
+ qp->ca_enabled = 0;
+ }
+ } else {
+ qp = cdev->data->queue_pairs[queue_pair_id];
+ qp->ca_enabled = 0;
+ }
+
+ return 0;
+}
+
/* Initialize and register event driver with DPDK Application */
static struct rte_eventdev_ops ssovf_ops = {
.dev_infos_get = ssovf_info_get,
@@ -755,6 +818,10 @@ static struct rte_eventdev_ops ssovf_ops = {
.timer_adapter_caps_get = ssovf_timvf_caps_get,
+ .crypto_adapter_caps_get = ssovf_crypto_adapter_caps_get,
+ .crypto_adapter_queue_pair_add = ssovf_crypto_adapter_qp_add,
+ .crypto_adapter_queue_pair_del = ssovf_crypto_adapter_qp_del,
+
.dev_selftest = test_eventdev_octeontx,
.dump = ssovf_dump,
--
2.25.1