From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70DF4458CD; Mon, 2 Sep 2024 11:56:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B67BB40A79; Mon, 2 Sep 2024 11:55:35 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by mails.dpdk.org (Postfix) with ESMTP id 3023240668 for ; Mon, 2 Sep 2024 11:55:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725270914; x=1756806914; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/JJHrApWYYQ6tKx4a0OfAnCIXBp3YvWAAvZymUVLI3o=; b=b57bOALnKxpSSURqdatEIwmtRzeBrHYER7tDoIVss3tU0BwDynjRXzLy JpZjVZ0450YPC4z54AzWXnLVWtL01JvmtSBCiKSr3dtuZDF7zUuY0CQBw /gpmudwvmmGa/UtDB7enoMIV/jHXh6leR4thcNakY+kAMckxm14kEsqVA UnKweTgYZd4x+SXbGLKDcNvHi9eLSs0n6OIgWY992N3RAmWXKndHWOWrE E3irebIUjW2BnVTaAMWCvJoDY4Cuqpu/tzEiQTVyZQ7HspFPlenVgAQHA 6AoXHIr17GclA4hsZ8BoS97TOBOBL2YPjrjDAtuyzoL67K1xkJEIuLNqT w==; X-CSE-ConnectionGUID: OtCZLkrhRDmUV38OqozY6Q== X-CSE-MsgGUID: rgc+2xejR1ye3F/h8bMQBw== X-IronPort-AV: E=McAfee;i="6700,10204,11182"; a="26747219" X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="26747219" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2024 02:55:13 -0700 X-CSE-ConnectionGUID: NZey5U8vTeCq9QbOXXkPOw== X-CSE-MsgGUID: Dn6Ek/HTQzStdoU9r65Z/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="64597936" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by fmviesa009.fm.intel.com with ESMTP; 02 Sep 2024 02:55:13 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: bruce.richardson@intel.com Subject: [PATCH v1 16/30] net/i40e/base: add X722 defines for input set mask Date: Mon, 2 Sep 2024 10:54:28 +0100 Message-ID: <2c22849aa93511b40815cb4bfe7678237ad580f8.1725270827.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Slawomir Laba Add X722 input set mask for RSS and flow director. X722 family is using different shifts on the registers from X710 NIC family. Signed-off-by: Slawomir Laba Signed-off-by: Anatoly Burakov --- drivers/net/i40e/base/i40e_type.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h index 2676d272c9..fe47f00ec9 100644 --- a/drivers/net/i40e/base/i40e_type.h +++ b/drivers/net/i40e/base/i40e_type.h @@ -1911,6 +1911,10 @@ struct i40e_lldp_variables { #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 /* INPUT SET MASK for RSS, flow director, and flexible payload */ +#define I40E_X722_L3_SRC_SHIFT 49 +#define I40E_X722_L3_SRC_MASK (0x3ULL << I40E_X722_L3_SRC_SHIFT) +#define I40E_X722_L3_DST_SHIFT 41 +#define I40E_X722_L3_DST_MASK (0x3ULL << I40E_X722_L3_DST_SHIFT) #define I40E_L3_SRC_SHIFT 47 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT) #define I40E_L3_V6_SRC_SHIFT 43 -- 2.43.5