On Tue, 1 Jul 2025, 20:21 , <uk7b@foxmail.com> wrote:

From: Sun Yuechi <sunyuechi@iscas.ac.cn>

This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".

The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defines V
intrinsics we can use rather than inline assembly on newer versions of
GCC (14.1.0+) and Clang (18.1.0+).

If the V extension and intrinsics are both present and we can detect
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>

Reviewed-by: Stanisław Kardach <stanislaw.kardach@gmail.com>

---
.mailmap | 1 +
config/riscv/meson.build | 25 +++++++++++++++++++++++++
lib/eal/riscv/include/rte_vect.h | 4 ++++
3 files changed, 30 insertions(+)

diff --git a/.mailmap b/.mailmap
index 8483d96ec5..21f5d7fb5e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1513,6 +1513,7 @@ Sunil Kumar Kori <skori@marvell.com> <skori@mavell.com> <sunil.kori@nxp.com>
Sunil Pai G <sunil.pai.g@intel.com>
Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>
Sun Jiajia <sunx.jiajia@intel.com>
+Sun Yuechi <sunyuechi@iscas.ac.cn> <uk7b@foxmail.com>
Sunyang Wu <sunyang.wu@jaguarmicro.com>
Surabhi Boob <surabhi.boob@intel.com>
Suyang Ju <sju@paloaltonetworks.com>
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 7562c6cb99..e3694cf2e6 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
endif
endforeach

+# check if we can do buildtime detection of extensions supported by the target
+riscv_extension_macros = false
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
+ message('Detected architecture extension test macros')
+ riscv_extension_macros = true
+else
+ warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')
+endif
+
+# detect extensions
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
+if (riscv_extension_macros and
+ (cc.get_define('__riscv_vector', args: machine_args) != ''))
+ if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
+ or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))
+ if (cc.compiles('''#include <riscv_vector.h>
+ int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))
+ message('Compiling with the V extension')
+ machine_args += ['-DRTE_RISCV_FEATURE_V']
+ endif
+ else
+ warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
+ endif
+endif
+
# apply flags
foreach flag: dpdk_flags
if flag.length() > 0
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
index 6df10fa8ee..a4357e266a 100644
--- a/lib/eal/riscv/include/rte_vect.h
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -11,6 +11,10 @@
#include "generic/rte_vect.h"
#include "rte_common.h"

+#ifdef RTE_RISCV_FEATURE_V
+#include <riscv_vector.h>
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
--
2.50.0