From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <thomas.monjalon@6wind.com>
Received: from mail-lf0-f53.google.com (mail-lf0-f53.google.com
 [209.85.215.53]) by dpdk.org (Postfix) with ESMTP id 573BAFAB9
 for <dev@dpdk.org>; Wed, 18 Jan 2017 17:25:25 +0100 (CET)
Received: by mail-lf0-f53.google.com with SMTP id n124so16141988lfd.2
 for <dev@dpdk.org>; Wed, 18 Jan 2017 08:25:25 -0800 (PST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=6wind-com.20150623.gappssmtp.com; s=20150623;
 h=from:to:cc:subject:date:message-id:user-agent:in-reply-to
 :references:mime-version:content-transfer-encoding;
 bh=YiXG1Rz9eplxJEwIkiVz7EGL9et9A5ke03b8M4qyg24=;
 b=jfm3WAi7ystCbLFfvKOKiDdbl2AueQqkH1p8j+5cca16p/x0W3bsF2r4cOPmxKu9Nt
 nTutWUdG0S/tqyP6MAx0fdpL+UV4vvUGV5aAo6MGmVm1geio3X6eq1g1ePp8+tpW9ta0
 dHSH/n/tbqsBL7IMgQKTtwjWwxoiJ+wQFTCHR/m7mTnHViXE2aq6bUx+9eIJ2Dddd22v
 d7zXsCAZhW0BT5GRW2J6Hjqsncnt6iaq/FfXfJUHlQRNExGN/gSaEwvJYSjlqM3IXHg5
 6VR29MMhKlIme1hMgN+Kbhvd1jJ2AwN5lrILPV+IAfow9v4zh8p9pu0jRQ/gqpNlL8d7
 sIFQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=1e100.net; s=20161025;
 h=x-gm-message-state:from:to:cc:subject:date:message-id:user-agent
 :in-reply-to:references:mime-version:content-transfer-encoding;
 bh=YiXG1Rz9eplxJEwIkiVz7EGL9et9A5ke03b8M4qyg24=;
 b=CvN2PWhkEJBIHNsd2k5/3bTdKq8Tu2fEWHdA/Fe9NbYRkblTp6fUihlpXiFgZuExDr
 XKUS+3+eCT4zann+aoVKnhSAHPjiagnIDq4lLsHbzbRKmQzzlaW0QezxmI57FAn89378
 bUqrcfSIGanwto/QvheY1BbKfBpnhqxGHcEaOHD4XoCV+XNwhFKdx2Uba5HMi/G/egiZ
 AKIAqXzyeEi5DCS+/6IfzhmWHM+Pq5hv1tdKYArPv0IC4/gA1yRjK/vVhB6QBUnMwORn
 bNnT8o21XyuY4mX158yG8nqCkFeIwFOakfERnzlZJD8cuSnmzfheQt/VMAf85BtkAYBu
 W/kQ==
X-Gm-Message-State: AIkVDXLTfLLK5Mk7NbzBTHhwBCbiqdumbyAhCfaIi/wIul7vsDCtMRt1f8ENFJqinJ3L25Cu
X-Received: by 10.25.228.157 with SMTP id x29mr1414761lfi.125.1484756724798;
 Wed, 18 Jan 2017 08:25:24 -0800 (PST)
Received: from xps13.localnet (184.203.134.77.rev.sfr.net. [77.134.203.184])
 by smtp.gmail.com with ESMTPSA id e12sm475236ljb.38.2017.01.18.08.25.23
 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);
 Wed, 18 Jan 2017 08:25:23 -0800 (PST)
From: Thomas Monjalon <thomas.monjalon@6wind.com>
To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com,
 jianbo.liu@linaro.org, viktorin@rehivetech.com,
 santosh.shukla@caviumnetworks.com
Date: Wed, 18 Jan 2017 17:25:22 +0100
Message-ID: <3075116.xAOueQvdyS@xps13>
User-Agent: KMail/4.14.10 (Linux/4.5.4-1-ARCH; KDE/4.14.11; x86_64; ; )
In-Reply-To: <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com>
References: <1484637244-7548-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <1484702502-25451-1-git-send-email-jerin.jacob@caviumnetworks.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 7Bit
Content-Type: text/plain; charset="us-ascii"
Subject: Re: [dpdk-dev] [PATCH v5 00/29] introduce I/O device memory
	read/write operations
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
X-List-Received-Date: Wed, 18 Jan 2017 16:25:25 -0000

2017-01-18 06:51, Jerin Jacob:
> Based on the discussion in the below-mentioned thread,
> http://dev.dpdk.narkive.com/DpIRqDuy/dpdk-dev-patch-v2-i40e-fix-eth-i40e-dev-init-sequence-on-thunderx
> 
> This patchset introduces 8-bit, 16-bit, 32bit, 64bit I/O device
> memory read/write operations along with the relaxed versions.
> 
> The weakly-ordered machine like ARM needs additional I/O barrier for
> device memory read/write access over PCI bus.
> By introducing the EAL abstraction for I/O device memory read/write access,
> The drivers can access I/O device memory in architecture-agnostic manner.
> 
> The relaxed version does not have additional I/O memory barrier, useful in
> accessing the device registers of integrated controllers which
> implicitly strongly ordered with respect to memory access.

Applied, thanks

Does it deserve an entry in the release notes?