From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FF56A0C4C; Tue, 5 Oct 2021 15:24:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BCFF41318; Tue, 5 Oct 2021 15:24:36 +0200 (CEST) Received: from new4-smtp.messagingengine.com (new4-smtp.messagingengine.com [66.111.4.230]) by mails.dpdk.org (Postfix) with ESMTP id 82AF241318 for ; Tue, 5 Oct 2021 15:24:35 +0200 (CEST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id 26B55580B1F; Tue, 5 Oct 2021 09:24:35 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Tue, 05 Oct 2021 09:24:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= gYjn5JR+3MApURIPolu/jXsqRTveoRopcXV34D0qnUI=; b=gRPq2MANXYK2lpUW lslCAyPopLHjT/NP+xQR9T0d527wC05xPJMXyIoGgLje7MyMvtXC6Vw0OW4RAejp VfCnJ7Ygs/q1cYgzAcgoZc34FfjpPOm0niYzs2+c0J05UQZXnnhxTVrHchWcok3T 6bGHLrm1feV8/i3D/EnaOPWiQqCkqpY4G+ITXsmOh2QLEvvktO6pu3W0kR2Ja8fJ gqZgr8kcZDD26rnSsc5i1HUQvVl+yD6lpxVZsgNZ+tLYaG64hCtDMyjWi94mNEZw cTWfz2ZhmU/QMvBAX3IlnFA/FXXtP7DHBajPAbpQjf+YBwdieOI7gS4qPwjec4AM +K4h3Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=gYjn5JR+3MApURIPolu/jXsqRTveoRopcXV34D0qn UI=; b=SsABE/5Kr9lhThLxvy3qpMpG94qAsjc3urJjYb+LkW55A12SOmryrsLTd tPHsySU0F2phaoFAIKrN9JRKzsRMjXZN0VKLPPeeAbIh8iFZPiDMmT/QDCHJyEXI tSbLODTql29XAYmaVOyttWzoZnXDo2u1HEIYNhS4zPCNn3DNAY9X+VcK7khs9gzg FkV0EmSCmTpZo5UbAzFLtKsEaUWRZbgBAjTPtVcN950C1YNaY/6H6wPGfR+UyGPF zQjeAc1WZQqTFfUehq3SETsGnyTpjCH7H45hDFyj9K84G7g+UbYCoL0nJy+GLDow 2MUDnM2n6AMR8Ho3QGOCgtanmNMSw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudelgedgieefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepudeggfdvfeduffdtfeeglefghfeukefgfffhueejtdetuedtjeeu ieeivdffgeehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 5 Oct 2021 09:24:25 -0400 (EDT) From: Thomas Monjalon To: Konstantin Ananyev Cc: dev@dpdk.org, xiaoyun.li@intel.com, anoobj@marvell.com, jerinj@marvell.com, ndabilpuram@marvell.com, adwivedi@marvell.com, shepard.siegel@atomicrules.com, ed.czeck@atomicrules.com, john.miller@atomicrules.com, irusskikh@marvell.com, ajit.khaparde@broadcom.com, somnath.kotur@broadcom.com, rahul.lakkireddy@chelsio.com, hemant.agrawal@nxp.com, sachin.saxena@oss.nxp.com, haiyue.wang@intel.com, johndale@cisco.com, hyonkim@cisco.com, qi.z.zhang@intel.com, xiao.w.wang@intel.com, humin29@huawei.com, yisen.zhuang@huawei.com, oulijun@huawei.com, beilei.xing@intel.com, jingjing.wu@intel.com, qiming.yang@intel.com, matan@nvidia.com, viacheslavo@nvidia.com, sthemmin@microsoft.com, longli@microsoft.com, heinrich.kuhn@corigine.com, kirankumark@marvell.com, andrew.rybchenko@oktetlabs.ru, mczekaj@marvell.com, jiawenwu@trustnetic.com, jianwang@trustnetic.com, maxime.coquelin@redhat.com, chenbo.xia@intel.com, ferruh.yigit@intel.com, mdr@ashroe.eu, jay.jayatheerthan@intel.com Date: Tue, 05 Oct 2021 15:24:23 +0200 Message-ID: <3078390.3ff9TgJ5vr@thomas> In-Reply-To: <20211004135603.20593-8-konstantin.ananyev@intel.com> References: <20211001140255.5726-1-konstantin.ananyev@intel.com> <20211004135603.20593-1-konstantin.ananyev@intel.com> <20211004135603.20593-8-konstantin.ananyev@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v4 7/7] ethdev: hide eth dev related structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 04/10/2021 15:56, Konstantin Ananyev: > Move rte_eth_dev, rte_eth_dev_data, rte_eth_rxtx_callback and related > data into private header (ethdev_driver.h). [...] > +/** > + * @internal > + * Structure used to hold information about the callbacks to be called for a > + * queue on RX and TX. > + */ > +struct rte_eth_rxtx_callback { > + struct rte_eth_rxtx_callback *next; > + union{ > + rte_rx_callback_fn rx; > + rte_tx_callback_fn tx; > + } fn; > + void *param; > +}; > + > +/** > + * @internal > + * The generic data structure associated with each ethernet device. > + * > + * Pointers to burst-oriented packet receive and transmit functions are > + * located at the beginning of the structure, along with the pointer to > + * where all the data elements for the particular device are stored in shared > + * memory. This split allows the function pointer and driver data to be per- > + * process, while the actual configuration data for the device is shared. > + */ > +struct rte_eth_dev { > + eth_rx_burst_t rx_pkt_burst; /**< Pointer to PMD receive function. */ > + eth_tx_burst_t tx_pkt_burst; /**< Pointer to PMD transmit function. */ > + eth_tx_prep_t tx_pkt_prepare; > + /**< Pointer to PMD transmit prepare function. */ > + eth_rx_queue_count_t rx_queue_count; > + /**< Get the number of used RX descriptors. */ > + eth_rx_descriptor_status_t rx_descriptor_status; > + /**< Check the status of a Rx descriptor. */ > + eth_tx_descriptor_status_t tx_descriptor_status; > + /**< Check the status of a Tx descriptor. */ Why not using the new struct rte_eth_fp_ops? > + > + /** > + * Next two fields are per-device data but *data is shared between > + * primary and secondary processes and *process_private is per-process > + * private. The second one is managed by PMDs if necessary. > + */ > + struct rte_eth_dev_data *data; /**< Pointer to device data. */ We should mention that "data" is shared between processes. > + void *process_private; /**< Pointer to per-process device data. */ > + const struct eth_dev_ops *dev_ops; /**< Functions exported by PMD */ > + struct rte_device *device; /**< Backing device */ > + struct rte_intr_handle *intr_handle; /**< Device interrupt handle */ > + /** User application callbacks for NIC interrupts */ > + struct rte_eth_dev_cb_list link_intr_cbs; > + /** > + * User-supplied functions called from rx_burst to post-process > + * received packets before passing them to the user > + */ > + struct rte_eth_rxtx_callback *post_rx_burst_cbs[RTE_MAX_QUEUES_PER_PORT]; > + /** > + * User-supplied functions called from tx_burst to pre-process > + * received packets before passing them to the driver for transmission. > + */ > + struct rte_eth_rxtx_callback *pre_tx_burst_cbs[RTE_MAX_QUEUES_PER_PORT]; > + enum rte_eth_dev_state state; /**< Flag indicating the port state */ > + void *security_ctx; /**< Context for security ops */ > + > + uint64_t reserved_64s[4]; /**< Reserved for future fields */ > + void *reserved_ptrs[4]; /**< Reserved for future fields */ > +} __rte_cache_aligned; > + > +struct rte_eth_dev_sriov; > +struct rte_eth_dev_owner; > + > +/** > + * @internal > + * The data part, with no function pointers, associated with each ethernet > + * device. This structure is safe to place in shared memory to be common > + * among different processes in a multi-process configuration. > + */ > +struct rte_eth_dev_data { > + char name[RTE_ETH_NAME_MAX_LEN]; /**< Unique identifier name */ > + > + void **rx_queues; /**< Array of pointers to RX queues. */ > + void **tx_queues; /**< Array of pointers to TX queues. */ > + uint16_t nb_rx_queues; /**< Number of RX queues. */ > + uint16_t nb_tx_queues; /**< Number of TX queues. */ > + > + struct rte_eth_dev_sriov sriov; /**< SRIOV data */ > + > + void *dev_private; > + /**< PMD-specific private data. > + * @see rte_eth_dev_release_port() > + */ > + > + struct rte_eth_link dev_link; /**< Link-level information & status. */ > + struct rte_eth_conf dev_conf; /**< Configuration applied to device. */ > + uint16_t mtu; /**< Maximum Transmission Unit. */ > + uint32_t min_rx_buf_size; > + /**< Common RX buffer size handled by all queues. */ > + > + uint64_t rx_mbuf_alloc_failed; /**< RX ring mbuf allocation failures. */ > + struct rte_ether_addr *mac_addrs; > + /**< Device Ethernet link address. > + * @see rte_eth_dev_release_port() > + */ > + uint64_t mac_pool_sel[ETH_NUM_RECEIVE_MAC_ADDR]; > + /**< Bitmap associating MAC addresses to pools. */ > + struct rte_ether_addr *hash_mac_addrs; > + /**< Device Ethernet MAC addresses of hash filtering. > + * @see rte_eth_dev_release_port() > + */ > + uint16_t port_id; /**< Device [external] port identifier. */ > + > + __extension__ > + uint8_t promiscuous : 1, > + /**< RX promiscuous mode ON(1) / OFF(0). */ > + scattered_rx : 1, > + /**< RX of scattered packets is ON(1) / OFF(0) */ > + all_multicast : 1, > + /**< RX all multicast mode ON(1) / OFF(0). */ > + dev_started : 1, > + /**< Device state: STARTED(1) / STOPPED(0). */ > + lro : 1, > + /**< RX LRO is ON(1) / OFF(0) */ > + dev_configured : 1; > + /**< Indicates whether the device is configured. > + * CONFIGURED(1) / NOT CONFIGURED(0). > + */ > + uint8_t rx_queue_state[RTE_MAX_QUEUES_PER_PORT]; > + /**< Queues state: HAIRPIN(2) / STARTED(1) / STOPPED(0). */ > + uint8_t tx_queue_state[RTE_MAX_QUEUES_PER_PORT]; > + /**< Queues state: HAIRPIN(2) / STARTED(1) / STOPPED(0). */ > + uint32_t dev_flags; /**< Capabilities. */ > + int numa_node; /**< NUMA node connection. */ > + struct rte_vlan_filter_conf vlan_filter_conf; > + /**< VLAN filter configuration. */ > + struct rte_eth_dev_owner owner; /**< The port owner. */ > + uint16_t representor_id; > + /**< Switch-specific identifier. > + * Valid if RTE_ETH_DEV_REPRESENTOR in dev_flags. > + */ > + > + pthread_mutex_t flow_ops_mutex; /**< rte_flow ops mutex. */ > + uint64_t reserved_64s[4]; /**< Reserved for future fields */ > + void *reserved_ptrs[4]; /**< Reserved for future fields */ > +} __rte_cache_aligned; > + > +/** > + * @internal > + * The pool of *rte_eth_dev* structures. The size of the pool > + * is configured at compile-time in the file. > + */ > +extern struct rte_eth_dev rte_eth_devices[]; Later we should add a function to configure the size of this array dynamically in the early DPDK init stage.