From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from m15-45.126.com (m15-45.126.com [220.181.15.45]) by dpdk.org (Postfix) with ESMTP id AF1706CC0 for ; Wed, 18 May 2016 18:15:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com; s=s110527; h=Date:From:Subject:MIME-Version:Message-ID; bh=VDW1W cJ6SVRBGwtY+7lOn+UgPkt5RbCdYItPglJ0Ic4=; b=ODCE/+ClBghMZio1kfahl PCd9jtceUNGkNRLeFTs9GU6dmPmAQOxXNYzM8bDWVbK7vuAE/wWaBQXgiMYRn89X 52CJnSaKc+qzCgoXjImIAZejH+mIV4F2ckqxNdla1/5gWNkC6riSprEIT3/O6POG AYSnXJD09RV6jcXV7037J0= Received: from zhangwqh$126.com ( [161.253.74.155, 54.215.2.217, 10.144.1.72] ) by ajax-webmail-wmsvr45 (Coremail) ; Thu, 19 May 2016 00:15:06 +0800 (CST) X-Originating-IP: [161.253.74.155, 54.215.2.217, 10.144.1.72] Date: Thu, 19 May 2016 00:15:06 +0800 (CST) From: =?GBK?B?1cXOsA==?= To: dev@dpdk.org X-Priority: 3 X-Mailer: Coremail Webmail Server Version SP_ntes V3.5 build 20160223(81157.8522) Copyright (c) 2002-2016 www.mailtech.cn 126com X-CM-CTRLDATA: 3pVl9mZvb3Rlcl9odG09ODEyOjU2 MIME-Version: 1.0 Message-ID: <340cd47b.eb8c.154c4a63296.Coremail.zhangwqh@126.com> X-Coremail-Locale: zh_CN X-CM-TRANSID: LcqowAAnLx8LlTxXvQywAA--.5043W X-CM-SenderInfo: x2kd0wxztkqiyswou0bp/1tbiWA5t6VWmL9myswABsX X-Coremail-Antispam: 1U5529EdanIXcx71UUUUU7vcSsGvfC2KfnxnUU== Content-Type: text/plain; charset=GBK Content-Transfer-Encoding: base64 X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-dev] EAL: memzone_reserve_aligned_thread_unsafe(): No more room in config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 May 2016 16:15:15 -0000 SGkgYWxsLCAKCgpXaGVuIHVzaW5nIGRwZGsgbXVsdGkgcHJvY2VzcyBjbGllbnQgc2VydmVyIGV4 YW1wbGUsIEkgY3JlYXRlIG1hbnkgY2xpZW50cy4gQWZ0ZXIgdGhlIG51bWJlciBvZiBjbGllbnRz IDEyMzksIEkgbWV0IHRoaXMgZXJyb3I6CgpFQUw6IG1lbXpvbmVfcmVzZXJ2ZV9hbGlnbmVkX3Ro cmVhZF91bnNhZmUoKTogTm8gbW9yZSByb29tIGluIGNvbmZpZwoKUklORzogQ2Fubm90IHJlc2Vy dmUgbWVtb3J5CgpFQUw6IEVycm9yIC0gZXhpdGluZyB3aXRoIGNvZGU6IDEKCiAgQ2F1c2U6IENh bm5vdCBjcmVhdGUgdHggcmluZyBxdWV1ZSBmb3IgY2xpZW50IDEyMzkKCkkgaGF2ZSAzMkcgaHVn ZSBwYWdlIG1lbW9yeS4gQ2FuIGFueW9uZSBnaXZlIHNvbWUgZ3VpZGFuY2UgaG93IHRvIGluY3Jl YXNlIHRoZSBtZW16b25lIG1lbW9yeT8gV2hpY2ggcGFyYW1ldGVyIHNob3VsZCBJIGFkanVzdCBp dD8g >From olivier.matz@6wind.com Wed May 18 18:27:51 2016 Return-Path: Received: from proxy.6wind.com (host.76.145.23.62.rev.coltfrance.com [62.23.145.76]) by dpdk.org (Postfix) with ESMTP id 11F918D37 for ; Wed, 18 May 2016 18:27:51 +0200 (CEST) Received: from glumotte.dev.6wind.com (unknown [10.16.0.195]) by proxy.6wind.com (Postfix) with ESMTP id 532DF201AB; Wed, 18 May 2016 18:26:14 +0200 (CEST) From: Olivier Matz To: dev@dpdk.org Cc: david.marchand@6wind.com, chaozhu@linux.vnet.ibm.com, yuanhan.liu@linux.intel.com, huawei.xie@intel.com Date: Wed, 18 May 2016 18:27:30 +0200 Message-Id: <1463588850-16601-1-git-send-email-olivier.matz@6wind.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1463479192-2488-6-git-send-email-olivier.matz@6wind.com> References: <1463479192-2488-6-git-send-email-olivier.matz@6wind.com> Subject: [dpdk-dev] [PATCH v3 5/7] eal/linux: mmap ioports on ppc64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 May 2016 16:27:51 -0000 On PPC64, the ioports are mapped in memory. Implement the missing part of ioport API for PPC64 when using uio. This may also work on other architectures but it has not been tested. Signed-off-by: David Marchand Signed-off-by: Olivier Matz --- Just resubmitting one patch for this patchset. v2 -> v3: - add missing close(), as pointed-out by David Marchand. lib/librte_eal/common/include/rte_pci.h | 4 +- lib/librte_eal/linuxapp/eal/eal_pci.c | 2 +- lib/librte_eal/linuxapp/eal/eal_pci_init.h | 10 +++ lib/librte_eal/linuxapp/eal/eal_pci_uio.c | 120 +++++++++++++++++++++++------ 4 files changed, 109 insertions(+), 27 deletions(-) diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index fd049d1..565bf38 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -105,9 +105,6 @@ extern struct pci_device_list pci_device_list; /**< Global list of PCI devices. /** Nb. of values in PCI resource format. */ #define PCI_RESOURCE_FMT_NVAL 3 -/** IO resource type: memory address space */ -#define IORESOURCE_MEM 0x00000200 - /** * A structure describing a PCI resource. */ @@ -518,6 +515,7 @@ int rte_eal_pci_write_config(const struct rte_pci_device *device, struct rte_pci_ioport { struct rte_pci_device *dev; uint64_t base; + uint64_t len; /* only filled for memory mapped ports */ }; /** diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c b/lib/librte_eal/linuxapp/eal/eal_pci.c index 1a93725..30e2328 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci.c @@ -193,7 +193,7 @@ pci_find_max_end_va(void) /* parse one line of the "resource" sysfs file (note that the 'line' * string is modified) */ -static int +int pci_parse_one_sysfs_resource(char *line, size_t len, uint64_t *phys_addr, uint64_t *end_addr, uint64_t *flags) { diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_init.h b/lib/librte_eal/linuxapp/eal/eal_pci_init.h index 7011753..f72a254 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_init.h +++ b/lib/librte_eal/linuxapp/eal/eal_pci_init.h @@ -36,12 +36,22 @@ #include "eal_vfio.h" +/** IO resource type: */ +#define IORESOURCE_IO 0x00000100 +#define IORESOURCE_MEM 0x00000200 + /* * Helper function to map PCI resources right after hugepages in virtual memory */ extern void *pci_map_addr; void *pci_find_max_end_va(void); +/* parse one line of the "resource" sysfs file (note that the 'line' + * string is modified) + */ +int pci_parse_one_sysfs_resource(char *line, size_t len, uint64_t *phys_addr, + uint64_t *end_addr, uint64_t *flags); + int pci_uio_alloc_resource(struct rte_pci_device *dev, struct mapped_pci_resource **uio_res); void pci_uio_free_resource(struct rte_pci_device *dev, diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_uio.c b/lib/librte_eal/linuxapp/eal/eal_pci_uio.c index ac449c5..fb04b65 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_uio.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci_uio.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -368,11 +369,11 @@ error: return -1; } +#if defined(RTE_ARCH_X86) int pci_uio_ioport_map(struct rte_pci_device *dev, int bar, struct rte_pci_ioport *p) { -#if defined(RTE_ARCH_X86) char dirname[PATH_MAX]; char filename[PATH_MAX]; int uio_num; @@ -411,81 +412,154 @@ pci_uio_ioport_map(struct rte_pci_device *dev, int bar, RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", start); p->base = start; + p->len = 0; return 0; +} #else - RTE_SET_USED(dev); - RTE_SET_USED(bar); - RTE_SET_USED(p); +int +pci_uio_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p) +{ + FILE *f; + char buf[BUFSIZ]; + char filename[PATH_MAX]; + uint64_t phys_addr, end_addr, flags; + int fd, i; + void *addr; + + /* open and read addresses of the corresponding resource in sysfs */ + snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource", + SYSFS_PCI_DEVICES, dev->addr.domain, dev->addr.bus, + dev->addr.devid, dev->addr.function); + f = fopen(filename, "r"); + if (f == NULL) { + RTE_LOG(ERR, EAL, "Cannot open sysfs resource: %s\n", + strerror(errno)); + return -1; + } + for (i = 0; i < bar + 1; i++) { + if (fgets(buf, sizeof(buf), f) == NULL) { + RTE_LOG(ERR, EAL, "Cannot read sysfs resource\n"); + goto error; + } + } + if (pci_parse_one_sysfs_resource(buf, sizeof(buf), &phys_addr, + &end_addr, &flags) < 0) + goto error; + if ((flags & IORESOURCE_IO) == 0) { + RTE_LOG(ERR, EAL, "BAR %d is not an IO resource\n", bar); + goto error; + } + snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/resource%d", + SYSFS_PCI_DEVICES, dev->addr.domain, dev->addr.bus, + dev->addr.devid, dev->addr.function, bar); + + /* mmap the pci resource */ + fd = open(filename, O_RDWR); + if (fd < 0) { + RTE_LOG(ERR, EAL, "Cannot open %s: %s\n", filename, + strerror(errno)); + goto error; + } + addr = mmap(NULL, end_addr + 1, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + close(fd); + if (addr == MAP_FAILED) { + RTE_LOG(ERR, EAL, "Cannot mmap IO port resource: %s\n", + strerror(errno)); + goto error; + } + + /* strangely, the base address is mmap addr + phys_addr */ + p->base = (uintptr_t)addr + phys_addr; + p->len = end_addr + 1; + RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%"PRIx64"\n", p->base); + fclose(f); + + return 0; + +error: + fclose(f); return -1; -#endif } +#endif void pci_uio_ioport_read(struct rte_pci_ioport *p, void *data, size_t len, off_t offset) { -#if defined(RTE_ARCH_X86) uint8_t *d; int size; - unsigned short reg = p->base + offset; + uintptr_t reg = p->base + offset; for (d = data; len > 0; d += size, reg += size, len -= size) { if (len >= 4) { size = 4; +#if defined(RTE_ARCH_X86) *(uint32_t *)d = inl(reg); +#else + *(uint32_t *)d = *(volatile uint32_t *)reg; +#endif } else if (len >= 2) { size = 2; +#if defined(RTE_ARCH_X86) *(uint16_t *)d = inw(reg); +#else + *(uint16_t *)d = *(volatile uint16_t *)reg; +#endif } else { size = 1; +#if defined(RTE_ARCH_X86) *d = inb(reg); - } - } #else - RTE_SET_USED(p); - RTE_SET_USED(data); - RTE_SET_USED(len); - RTE_SET_USED(offset); + *d = *(volatile uint8_t *)reg; #endif + } + } } void pci_uio_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset) { -#if defined(RTE_ARCH_X86) const uint8_t *s; int size; - unsigned short reg = p->base + offset; + uintptr_t reg = p->base + offset; for (s = data; len > 0; s += size, reg += size, len -= size) { if (len >= 4) { size = 4; +#if defined(RTE_ARCH_X86) outl_p(*(const uint32_t *)s, reg); +#else + *(volatile uint32_t *)reg = *(const uint32_t *)s; +#endif } else if (len >= 2) { size = 2; +#if defined(RTE_ARCH_X86) outw_p(*(const uint16_t *)s, reg); +#else + *(volatile uint16_t *)reg = *(const uint16_t *)s; +#endif } else { size = 1; +#if defined(RTE_ARCH_X86) outb_p(*s, reg); - } - } #else - RTE_SET_USED(p); - RTE_SET_USED(data); - RTE_SET_USED(len); - RTE_SET_USED(offset); + *(volatile uint8_t *)reg = *s; #endif + } + } } int pci_uio_ioport_unmap(struct rte_pci_ioport *p) { - RTE_SET_USED(p); #if defined(RTE_ARCH_X86) + RTE_SET_USED(p); /* FIXME close intr fd ? */ return 0; #else - return -1; + return munmap((void *)(uintptr_t)p->base, p->len); #endif } -- 2.8.0.rc3