From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A705AA2F18 for ; Thu, 3 Oct 2019 15:04:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D5A521C0AA; Thu, 3 Oct 2019 15:04:42 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 7FE3E1BEF5 for ; Thu, 3 Oct 2019 15:04:39 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Oct 2019 06:04:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,252,1566889200"; d="scan'208";a="367035260" Received: from irsmsx154.ger.corp.intel.com ([163.33.192.96]) by orsmga005.jf.intel.com with ESMTP; 03 Oct 2019 06:04:36 -0700 Received: from irsmsx101.ger.corp.intel.com ([169.254.1.129]) by IRSMSX154.ger.corp.intel.com ([169.254.12.160]) with mapi id 14.03.0439.000; Thu, 3 Oct 2019 14:04:36 +0100 From: "Trahe, Fiona" To: "Dybkowski, AdamX" , "dev@dpdk.org" , "Kusztal, ArkadiuszX" , "akhil.goyal@nxp.com" CC: "Trahe, Fiona" Thread-Topic: [PATCH v2 3/3] crypto/qat: handle Single Pass Crypto Requests on GEN3 QAT Thread-Index: AQHVdUtN7UG4AM0PgUKYjmwskEWJFKdI6ggA Date: Thu, 3 Oct 2019 13:04:35 +0000 Message-ID: <348A99DA5F5B7549AA880327E580B4358982AD95@IRSMSX101.ger.corp.intel.com> References: <20190906144751.3420-1-adamx.dybkowski@intel.com> <20190927154739.26404-1-adamx.dybkowski@intel.com> <20190927154739.26404-4-adamx.dybkowski@intel.com> In-Reply-To: <20190927154739.26404-4-adamx.dybkowski@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDA4MWY1NmQtYjU3NC00M2RkLTg4YTAtMTI2OWEzZDBjYzNiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiU3h1dkNSb2g0OENrZDFpa2tVSXhqSTBEOWx6Q2NMMTlFVkdwNXN5QU1xaCs2TFpcL0pZSDVEblZFcVwvc2ZNcDgyIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 3/3] crypto/qat: handle Single Pass Crypto Requests on GEN3 QAT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Adam, > -----Original Message----- > From: Dybkowski, AdamX > Sent: Friday, September 27, 2019 4:48 PM > To: dev@dpdk.org; Trahe, Fiona ; Kusztal, Arkadius= zX > ; akhil.goyal@nxp.com > Cc: Dybkowski, AdamX > Subject: [PATCH v2 3/3] crypto/qat: handle Single Pass Crypto Requests on= GEN3 QAT >=20 > This patch improves the performance of AES GCM by using > the Single Pass Crypto Request functionality when running > on GEN3 QAT. Falls back to classic chained mode on older > hardware. >=20 > Signed-off-by: Adam Dybkowski > --- > doc/guides/rel_notes/release_19_11.rst | 7 +++ > drivers/crypto/qat/qat_sym.c | 13 +++- > drivers/crypto/qat/qat_sym_session.c | 86 ++++++++++++++++++++++++-- > drivers/crypto/qat/qat_sym_session.h | 9 ++- > 4 files changed, 107 insertions(+), 8 deletions(-) >=20 > diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_note= s/release_19_11.rst > index 573683da4..4817b7f23 100644 > --- a/doc/guides/rel_notes/release_19_11.rst > +++ b/doc/guides/rel_notes/release_19_11.rst > @@ -61,6 +61,13 @@ New Features > Added stateful decompression support in the Intel QuickAssist Technolo= gy PMD. > Please note that stateful compression is not supported. >=20 > +* **Enabled Single Pass GCM acceleration on QAT GEN3.** > + > + Added support for Single Pass GCM, available on QAT GEN3 only (Intel > + QuickAssist Technology C4xxx). It is automatically chosen instead of t= he > + classic chained mode when running on QAT GEN3, significantly improving > + the performance of AES GCM operations. > + > Removed Items > ------------- >=20 > diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c > index 46ef27a6d..5ff4aa1e5 100644 > --- a/drivers/crypto/qat/qat_sym.c > +++ b/drivers/crypto/qat/qat_sym.c > @@ -1,5 +1,5 @@ > /* SPDX-License-Identifier: BSD-3-Clause > - * Copyright(c) 2015-2018 Intel Corporation > + * Copyright(c) 2015-2019 Intel Corporation > */ >=20 > #include > @@ -12,6 +12,7 @@ >=20 > #include "qat_sym.h" >=20 > + > /** Decrypt a single partial block > * Depends on openssl libcrypto > * Uses ECB+XOR to do CFB encryption, same result, more performant > @@ -195,7 +196,8 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, > rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req)); > qat_req->comn_mid.opaque_data =3D (uint64_t)(uintptr_t)op; > cipher_param =3D (void *)&qat_req->serv_specif_rqpars; > - auth_param =3D (void *)((uint8_t *)cipher_param + sizeof(*cipher_param)= ); > + auth_param =3D (void *)((uint8_t *)cipher_param + > + ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET); >=20 > if (ctx->qat_cmd =3D=3D ICP_QAT_FW_LA_CMD_HASH_CIPHER || > ctx->qat_cmd =3D=3D ICP_QAT_FW_LA_CMD_CIPHER_HASH) { > @@ -593,6 +595,13 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, > qat_req->comn_mid.dest_data_addr =3D dst_buf_start; > } >=20 > + /* Handle Single-Pass GCM */ > + if (ctx->is_single_pass) { > + cipher_param->spc_aad_addr =3D op->sym->aead.aad.phys_addr; > + cipher_param->spc_auth_res_addr =3D > + op->sym->aead.digest.phys_addr; > + } > + > #if RTE_LOG_DP_LEVEL >=3D RTE_LOG_DEBUG > QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req, > sizeof(struct icp_qat_fw_la_bulk_req)); > diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qa= t_sym_session.c > index e5167b3fa..7d0f4a69d 100644 > --- a/drivers/crypto/qat/qat_sym_session.c > +++ b/drivers/crypto/qat/qat_sym_session.c > @@ -450,7 +450,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *= dev, > break; > case ICP_QAT_FW_LA_CMD_CIPHER_HASH: > if (xform->type =3D=3D RTE_CRYPTO_SYM_XFORM_AEAD) { > - ret =3D qat_sym_session_configure_aead(xform, > + ret =3D qat_sym_session_configure_aead(dev, xform, > session); > if (ret < 0) > return ret; > @@ -467,7 +467,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *= dev, > break; > case ICP_QAT_FW_LA_CMD_HASH_CIPHER: > if (xform->type =3D=3D RTE_CRYPTO_SYM_XFORM_AEAD) { > - ret =3D qat_sym_session_configure_aead(xform, > + ret =3D qat_sym_session_configure_aead(dev, xform, > session); > if (ret < 0) > return ret; > @@ -503,6 +503,72 @@ qat_sym_session_set_parameters(struct rte_cryptodev = *dev, > return 0; > } >=20 > +static int > +qat_sym_session_handle_single_pass(struct qat_sym_dev_private *internals= , > + struct qat_sym_session *session, > + struct rte_crypto_aead_xform *aead_xform) > +{ > + enum qat_device_gen qat_dev_gen =3D internals->qat_dev->qat_dev_gen; > + > + if (qat_dev_gen =3D=3D QAT_GEN3 && > + aead_xform->iv.length =3D=3D QAT_AES_GCM_SPC_IV_SIZE) { > + /* Use faster Single-Pass GCM */ [Fiona] Need to set min_qat_dev_gen in session here.=20 Crypto sessions can be built independently of the device. Catches a very un= likely corner case. If e.g. platform had a gen1 and gen3 device, did the session init on the ge= n3, then attached it to an op sent to gen1, This min_qat_dev_gen would catch it. Same situation possible with ZUC so we= added that check then.