From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 96DDDA045E for ; Tue, 28 May 2019 07:40:29 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2A6583576; Tue, 28 May 2019 07:40:28 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 933B89E4; Tue, 28 May 2019 07:40:25 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 May 2019 22:40:24 -0700 X-ExtLoop1: 1 Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga002.jf.intel.com with ESMTP; 27 May 2019 22:40:24 -0700 Received: from cdsmsx101.ccr.corp.intel.com (172.17.3.36) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 27 May 2019 22:40:23 -0700 Received: from cdsmsx102.ccr.corp.intel.com ([169.254.2.223]) by CDSMSX101.ccr.corp.intel.com ([169.254.1.179]) with mapi id 14.03.0415.000; Tue, 28 May 2019 13:40:20 +0800 From: "Wei, Dan" To: "Xu, Rosen" , "dev@dpdk.org" CC: "Yigit, Ferruh" , "Chen, Santos" , "stable@dpdk.org" Thread-Topic: [DPDK] net/ipn3ke: modifications on AFU configurations Thread-Index: AQHVEdXIbLeoMS5lv0ql7bEJTZxMyaZ5EdyAgAatZKA= Date: Tue, 28 May 2019 05:40:20 +0000 Message-ID: <35413AA7DC893F4FA6679F94DEE6B7E73C22B6F6@CDSMSX102.ccr.corp.intel.com> References: <1558710030-46746-1-git-send-email-dan.wei@intel.com> <0E78D399C70DA940A335608C6ED296D73A778684@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <0E78D399C70DA940A335608C6ED296D73A778684@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmNjN2ZiYzUtZjc1My00NjVmLTgyMDctMDlhNGEyOWIzODFkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibTQzSFRiT3ZRbnhDYkJ1dTNieHUxOGJYZityY01TdzZnWWRCVjJlXC93UXJcL1VybzhJcmJPdnJneVl6TjBTeVVcLyJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.17.6.105] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [DPDK] net/ipn3ke: modifications on AFU configurations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi,=20 -----Original Message----- From: Xu, Rosen=20 Sent: Friday, May 24, 2019 11:07 AM To: Wei, Dan ; dev@dpdk.org Cc: Yigit, Ferruh ; Chen, Santos ; stable@dpdk.org Subject: RE: [DPDK] net/ipn3ke: modifications on AFU configurations Hi, > > -----Original Message----- > > From: Wei, Dan > > Sent: Friday, May 24, 2019 23:01 > > To: dev@dpdk.org > > Cc: Yigit, Ferruh ; Chen, Santos=20 > > ; Wei, Dan ; Xu, Rosen=20 > > ; stable@dpdk.org > > Subject: [DPDK] net/ipn3ke: modifications on AFU configurations > Pls figure out exact modification in title. > My understanding this patch is for AFU register access, is it so? Besides AFU register access, there are other modifications listed in the co= mmit message body. > > Modify AFU configurations for new Blue Bitstream of A10 on N3000 card: > > - AFU register access > > - AFU configuration should wait until the HW set the INIT_DONE flag > > - Refine log for debug > Could you take more description about this modification? - AFU register access: RTL changes the UPL base address and the read/write = commands of register indirect access - AFU configuration should wait until the HW set the INIT_DONE flag: The re= set lasts for a long time in the new version of BBS. AFU configuration should wait for the end of reset with the setting of t= he INIT_DONE flag.=20 - Refine log for debug: print UPL_version not only for vBNG bit stream, but= also for other bit streams.=20 =20 > > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > > Cc: rosen.xu@intel.com > > Cc: stable@dpdk.org > >=20 > > Signed-off-by: Dan Wei > > --- > > drivers/net/ipn3ke/ipn3ke_ethdev.c | 8 ++++++--=20 > > drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++---- > > drivers/net/ipn3ke/ipn3ke_flow.c | 1 + > > 3 files changed, 12 insertions(+), 6 deletions(-) > >=20 > > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c > > b/drivers/net/ipn3ke/ipn3ke_ethdev.c > > index 9079b57..cadfadd 100644 > > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > > @@ -223,11 +223,15 @@ > > "LineSideMACType", &mac_type); > > hw->retimer.mac_type =3D (int)mac_type; > >=20 > > + /* Wait until init done */ > > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) !=3D 0x3) > > + ; > > + > > + IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > > IPN3KE_READ_REG(hw, 0)); > > + > > if (afu_dev->id.uuid.uuid_low =3D=3D IPN3KE_UUID_VBNG_LOW && > > afu_dev->id.uuid.uuid_high =3D=3D IPN3KE_UUID_VBNG_HIGH) { > > ipn3ke_hw_cap_init(hw); > > - IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > > - IPN3KE_READ_REG(hw, 0)); > Why remove this debug output? The debug output isn't removed but moved up. Print UPL_version not only for= vBNG bit stream, but also for other bit streams. > > /* Reset FPGA IP */ > > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1); diff --git=20 > > a/drivers/net/ipn3ke/ipn3ke_ethdev.h > > b/drivers/net/ipn3ke/ipn3ke_ethdev.h > > index bfda9d5..686c12f 100644 > > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h > > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h > > @@ -344,7 +344,6 @@ static inline uint32_t ipn3ke_read_addr(volatile=20 > > void > > *addr) > >=20 > > #define WCMD 0x8000000000000000 > > #define RCMD 0x4000000000000000 > > -#define UPL_BASE 0x10000 > > static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw, > > uint32_t addr) > > { > > @@ -355,13 +354,13 @@ static inline uint32_t=20 > > _ipn3ke_indrct_read(struct ipn3ke_hw *hw, > >=20 > > word_offset =3D (addr & 0x1FFFFFF) >> 2; > > indirect_value =3D RCMD | word_offset << 32; > > - indirect_addrs =3D hw->hw_addr + (uint32_t)(UPL_BASE | 0x10);=20 > > + indirect_addrs =3D hw->hw_addr + (uint32_t)(0x30); > >=20 > > rte_delay_us(10); > >=20 > > rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); > >=20 > > - indirect_addrs =3D hw->hw_addr + (uint32_t)(UPL_BASE | 0x18); > > + indirect_addrs =3D hw->hw_addr + (uint32_t)(0x38); > > while ((read_data >> 32) !=3D 1) > > read_data =3D rte_read64(indirect_addrs); > >=20 > > @@ -377,7 +376,7 @@ static inline void _ipn3ke_indrct_write(struct=20 > > ipn3ke_hw *hw, > >=20 > > word_offset =3D (addr & 0x1FFFFFF) >> 2; > > indirect_value =3D WCMD | word_offset << 32 | value; > > - indirect_addrs =3D hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > > + indirect_addrs =3D hw->hw_addr + (uint32_t)(0x30); > >=20 > > rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); > > rte_delay_us(10); > > @@ -411,6 +410,7 @@ static inline void _ipn3ke_indrct_write(struct=20 > > ipn3ke_hw *hw, > > (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm)) > >=20 > > /* Byte address of IPN3KE internal module */ > > +#define IPN3KE_INIT_DONE (0x204) > > #define IPN3KE_TM_VERSION (IPN3KE_QM_OFFSET + 0x00= 00) > > #define IPN3KE_TM_SCRATCH (IPN3KE_QM_OFFSET + 0x00= 04) > > #define IPN3KE_TM_STATUS (IPN3KE_QM_OFFSET + 0x00= 08) > > @@ -500,6 +500,7 @@ static inline void _ipn3ke_indrct_write(struct=20 > > ipn3ke_hw *hw, > > #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET = + 0x0400) > >=20 > > #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 > > + 0x0000) > > +#define IPN3KE_CLF_EM_SCRATCH (IPN3KE_CLASSIFY_OFFSET + 0x40000 > > + 0x0004) > > #define IPN3KE_CLF_EM_NUM (IPN3KE_CLASSIFY_OFFSET + 0x40000 = + > > 0x0008) > > #define IPN3KE_CLF_EM_KEY_WDTH (IPN3KE_CLASSIFY_OFFSET + > > 0x40000 + 0x000C) > > #define IPN3KE_CLF_EM_RES_WDTH (IPN3KE_CLASSIFY_OFFSET + > > 0x40000 + 0x0010) > > diff --git a/drivers/net/ipn3ke/ipn3ke_flow.c > > b/drivers/net/ipn3ke/ipn3ke_flow.c > > index e5937df..ff9f064 100644 > > --- a/drivers/net/ipn3ke/ipn3ke_flow.c > > +++ b/drivers/net/ipn3ke/ipn3ke_flow.c > > @@ -1360,6 +1360,7 @@ int ipn3ke_flow_init(void *dev) > > IPN3KE_CLF_EM_NUM, > > 0, > > 0xFFFFFFFF); > > + IPN3KE_AFU_PMD_DEBUG("IPN3KE_CLF_EN_NUM: %x\n", hw- > > >flow_max_entries); > > hw->flow_num_entries =3D 0; > >=20 > > return 0; > > -- > > 1.8.3.1