From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9134A0C4E; Thu, 21 Oct 2021 16:26:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A41BB41202; Thu, 21 Oct 2021 16:26:58 +0200 (CEST) Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) by mails.dpdk.org (Postfix) with ESMTP id 71A2E4118E for ; Thu, 21 Oct 2021 16:26:57 +0200 (CEST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 22B183200495; Thu, 21 Oct 2021 10:26:55 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Thu, 21 Oct 2021 10:26:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= MUk6WDWkfLcJ2jFMvSxb91oW2sdGiPcJuIzZtdNpry8=; b=G0SeOVQuOFK28lmt ag3OY+tZ52sYBdYOYz7oqgnpv8FHXNCPxNSwvQ6PxiMz+QbETQ5L5kiL4LVfge1z o5qkCR/+lz7se7bhKpe3jUHg8C7sJH0x7+aXxqIZbk+KGMX49dmyQP2UgRtLLGn2 s/CzkfKxPSuEhffGQbltoOpFBgUnG0NKm8VXbxm0gJdKoXVefZuWX9vn47/+nwU8 ct21CiSmnm9FYVMIWvobqJFvBWMLS6tWIAUgEqwdoIQs6vmhWiHP+FPGhhuQPoF+ a2DUiTkGrblxXGyybHIWTmYPrnuncQpDUnAiyRDGmRRlNJmoviGgJHfaO2pAdZoU OT7t9g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=MUk6WDWkfLcJ2jFMvSxb91oW2sdGiPcJuIzZtdNpr y8=; b=H/l74erdCMHBdAicbCcZ2gQxRvHjskfRmLFfa2A2oBwoT46w2SYPAK8m1 jzkqAN3wXewXqt2f40jcsjHxZZpJRoFsc9yJC/fYsSH4Fx9KBvSHtg66go9USrsU dHMuGO29JFcj2i1WN4BF+nQbSpE4wYYfbb4z+fDOCSANNjMUXAMLFu2pOTrA3tHX 3gshG0LClXKRFgR9sJvvPigtilxGUEwny60zL4KzTvbt94WmXE25fuQadSE8gH4Y iVvBr/5NALgU+UXIcpbFrrrU4/qz+6kxrNuUH8patFo+ZNtQFZ1QKaN6c2s+Lzl8 1SvqcIr+9VeLrIX85DScpXBETazbg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrvddviedgjeehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepudeggfdvfeduffdtfeeglefghfeukefgfffhueejtdetuedtjeeu ieeivdffgeehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 21 Oct 2021 10:26:53 -0400 (EDT) From: Thomas Monjalon To: Michael Baum Cc: dev@dpdk.org, Matan Azrad Date: Thu, 21 Oct 2021 16:26:51 +0200 Message-ID: <3610969.Wcvq156IVY@thomas> In-Reply-To: <20211019205602.3188203-1-michaelba@nvidia.com> References: <20211006220350.2357487-1-michaelba@nvidia.com> <20211019205602.3188203-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v3 00/18] mlx5: sharing global MR cache between drivers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Michael Baum (18): > net/mlx5/windows: fix miss callback register for mem event > common/mlx5: share basic probing with the internal drivers > common/mlx5: share common definitions > common/mlx5: share memory related devargs > net/mlx5/windows: rearrange probing code > common/mlx5: move basic probing functions to common > net/mlx5: remove redundant flag in device config > common/mlx5: share device context object > common/mlx5: add ROCE disable in context device creation > common/mlx5: share the protection domain object > common/mlx5: share the HCA capabilities handle > net/mlx5: remove redundancy in MR file > common/mlx5: add MR ctrl init function > common/mlx5: add global MR cache create function > common/mlx5: share MR top-half search function > common/mlx5: share MR management > common/mlx5: support device DMA map and unmap > common/mlx5: share MR mempool registration Applied, thanks.