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From: Thomas Monjalon <thomas@monjalon.net>
To: Tal Shnaiderman <talshn@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	stable@dpdk.org, Shahaf Shuler <shahafs@nvidia.com>,
	Slava Ovsiienko <viacheslavo@nvidia.com>,
	Matan Azrad <matan@nvidia.com>
Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2] common/mlx5: split relaxed ordering set for read and write
Date: Wed, 04 Nov 2020 19:04:50 +0100	[thread overview]
Message-ID: <3639485.kFSM30kCNj@thomas> (raw)
In-Reply-To: <MW2PR12MB24922A2FA95E3857F53C45C1DF110@MW2PR12MB2492.namprd12.prod.outlook.com>

03/11/2020 10:15, Matan Azrad:
> From: Tal Shnaiderman
> > The current DevX implementation of the relaxed ordering feature is enabling
> > relaxed ordering usage only if both relaxed ordering read AND write are
> > supported.  In that case both relaxed ordering read and write are activated.
> > 
> > This commit will optimize the usage of relaxed ordering by enabling it when
> > the read OR write features are supported.  Each relaxed ordering type will be
> > activated according to its own capability bit.
> > 
> > This will align the DevX flow with the verbs implementation of ibv_reg_mr
> > when using the flag IBV_ACCESS_RELAXED_ORDERING
> > 
> > Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions")
> > Cc: stable@dpdk.org
> > 
> > Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>

Applied, thanks

Note: adding "PCI" to distinguish from memory relaxed ordering.



      reply	other threads:[~2020-11-04 18:04 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-30 12:26 [dpdk-dev] [PATCH] " Tal Shnaiderman
2020-11-03  8:51 ` [dpdk-dev] [PATCH v2] " Tal Shnaiderman
2020-11-03  9:15   ` Matan Azrad
2020-11-04 18:04     ` Thomas Monjalon [this message]

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