From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C47E0A04B1; Wed, 4 Nov 2020 19:04:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 40E392BEA; Wed, 4 Nov 2020 19:04:57 +0100 (CET) Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id 6CE2F100C; Wed, 4 Nov 2020 19:04:54 +0100 (CET) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.nyi.internal (Postfix) with ESMTP id C52B45C0175; Wed, 4 Nov 2020 13:04:52 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 04 Nov 2020 13:04:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= 5X5h4jUy8Gt2ejDaK52t5s+5UJKG6xhJyxbPFIa7yc0=; b=cnDrOfna0eoGh39Z zrgFCXOOMEzxezAn8tVsGnPX+TZay4coh58mL3rPdAbD4sqJLbTP0cwpDht7doLj Pajz1Rz3k5xdwESsHDHKsFetDmzCKvvDwjRlnk3hYgkigJAKr5p1SgkfjglJMuhJ g0DiTme3SfAydeK6XA8oDG01gpiGTqkPfyJ9LeoVXcRwF3+Tk8G1iMgEXr4pLYGJ u1/yjSbtqjrcTT+C/UBkp9JX+qavcudi7/j92HnOmxPcziHpl/LCDhNSoGqomTs1 WiM3ffNRyOZ2To60lvFLWE/7zDJXq0XP4lJHQ/q8/VoO/3jjuEXHAvaRUwhMbSte 1EPaPQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=5X5h4jUy8Gt2ejDaK52t5s+5UJKG6xhJyxbPFIa7y c0=; b=OY2A6j+aXcSi6mOR6JzI3mS8jPvLortAANf7ukdRsiuwwR351sor7uvxb 9Tsdz30PyHlxX5dYUgNnkT1405xtvJxQYz+l0Kr66PNA+xMAKdrcmxhAWSdKKxCG y05x/lFSDYoCjt0TAnP5TTXreGI+f0Wj4a0zzAnuWFrKy4hL5g2nnd4cXu8H/H+4 xIZVpZNHd4qErPzDkFo222wh4/EhqACriDb6uClWS7314N9IpBOesz2JPCLbre6T BaH6KYot2M0G6wtOj4AoxIqzb/rQimfZS/orDJ9bjTybY+bc4iX8NO+ykLVkpTYB RnMchhxc+OmI5A8I9v+7sosNvZewA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedruddthedguddtlecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhm rghsucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenuc ggtffrrghtthgvrhhnpedugefgvdefudfftdefgeelgffhueekgfffhfeujedtteeutdej ueeiiedvffegheenucfkphepjeejrddufeegrddvtdefrddukeegnecuvehluhhsthgvrh fuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepthhhohhmrghssehmohhnjhgr lhhonhdrnhgvth X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id CE29F3064680; Wed, 4 Nov 2020 13:04:51 -0500 (EST) From: Thomas Monjalon To: Tal Shnaiderman Cc: "dev@dpdk.org" , stable@dpdk.org, Shahaf Shuler , Slava Ovsiienko , Matan Azrad Date: Wed, 04 Nov 2020 19:04:50 +0100 Message-ID: <3639485.kFSM30kCNj@thomas> In-Reply-To: References: <20201030122644.15616-1-talshn@nvidia.com> <20201103085122.8348-1-talshn@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2] common/mlx5: split relaxed ordering set for read and write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 03/11/2020 10:15, Matan Azrad: > From: Tal Shnaiderman > > The current DevX implementation of the relaxed ordering feature is enabling > > relaxed ordering usage only if both relaxed ordering read AND write are > > supported. In that case both relaxed ordering read and write are activated. > > > > This commit will optimize the usage of relaxed ordering by enabling it when > > the read OR write features are supported. Each relaxed ordering type will be > > activated according to its own capability bit. > > > > This will align the DevX flow with the verbs implementation of ibv_reg_mr > > when using the flag IBV_ACCESS_RELAXED_ORDERING > > > > Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions") > > Cc: stable@dpdk.org > > > > Signed-off-by: Tal Shnaiderman > Acked-by: Matan Azrad Applied, thanks Note: adding "PCI" to distinguish from memory relaxed ordering.