From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id A52FD7CD8 for ; Wed, 17 Jan 2018 14:46:54 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 1A6D820DA6; Wed, 17 Jan 2018 08:46:54 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute1.internal (MEProxy); Wed, 17 Jan 2018 08:46:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc; s=mesmtp; bh=0g1fPO9c5mefpdWk/nc5usSILK Q6ObY/Isb/VjQA1FI=; b=RA6v9vfXPq5dFLEbd2ZmR32P5NL3AvmAp2J+qVOa45 xiAUz6/yX/duA5NH1yCpoUOKgahotMdK0u/Ue9cHcU85BbRpeKPvZVigNWYan8tZ vwohze/SCvHEdlayh+cfFfSt4eLq26jiQVJUyPla/qzUpD8eNhaO1n1ZQJDvLt/z g= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=0g1fPO 9c5mefpdWk/nc5usSILKQ6ObY/Isb/VjQA1FI=; b=g/k3KuAcATXDHidsilb2Nb Tn0uHnzOdSP81umFpJRVhXSqqr8sQsSdSVXmoq7ClUKFufPAwfsIkTMHZiM8QrPo 2LSGxp+H/BBA0vDXxN75nMxciM0EOl+r9pdTihUAiEth5BnmmbJe23t486RF7B/L 28D3Kxz3QZDouVL9uIgav6uwcowDUKThGvfKPqblvWJ+1OMEz0F1rs+3HZMq8340 sl/PPTEco52lFvfpfX/xwJ3ldGujzoZ9aXScdVEE2qrQy6rBYJboedMymfzVjpPU H0J+DH4f/bHaMdLh5HjsMZS/cL6sUhAgqXZ8ChoNoMeNSvWuG5TFuELxX0QuthEw == X-ME-Sender: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id B00117E322; Wed, 17 Jan 2018 08:46:53 -0500 (EST) From: Thomas Monjalon To: Jianbo Liu , Andrew Rybchenko , Yongseok Koh Cc: dev@dpdk.org, adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com, jerin.jacob@caviumnetworks.com, konstantin.ananyev@intel.com, bruce.richardson@intel.com, Chao Zhu Date: Wed, 17 Jan 2018 14:46:21 +0100 Message-ID: <3720864.2redlIt54T@xps> In-Reply-To: <20180116091040.GA15629@arm.com> References: <20171227042824.33373-1-yskoh@mellanox.com> <20180116091040.GA15629@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v2 1/8] eal: introduce DMA memory barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Jan 2018 13:46:54 -0000 16/01/2018 10:10, Jianbo Liu: > The 01/16/2018 10:49, Andrew Rybchenko wrote: > > On 01/16/2018 04:10 AM, Yongseok Koh wrote: > > >This commit introduces rte_dma_wmb() and rte_dma_rmb(), in order to > > >guarantee the ordering of coherent shared memory between the CPU and a DMA > > >capable device. > > > > > >Signed-off-by: Yongseok Koh > > >--- > > > lib/librte_eal/common/include/generic/rte_atomic.h | 18 ++++++++++++++++++ > > > 1 file changed, 18 insertions(+) > > > > > >diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h > > >index 16af5ca57..2e0503ce6 100644 > > >--- a/lib/librte_eal/common/include/generic/rte_atomic.h > > >+++ b/lib/librte_eal/common/include/generic/rte_atomic.h > > >@@ -98,6 +98,24 @@ static inline void rte_io_wmb(void); > > > */ > > > static inline void rte_io_rmb(void); > > >+/** > > >+ * Write memory barrier for coherent memory between lcore and IO device > > >+ * > > >+ * Guarantees that the STORE operations on coherent memory that > > >+ * precede the rte_dma_wmb() call are visible to I/O device before the > > >+ * STORE operations that follow it. > > >+ */ > > >+static inline void rte_dma_wmb(void); > > >+ > > >+/** > > >+ * Read memory barrier for coherent memory between lcore and IO device > > >+ * > > >+ * Guarantees that the LOAD operations on coherent memory updated by > > >+ * IO device that precede the rte_dma_rmb() call are visible to CPU > > >+ * before the LOAD operations that follow it. > > >+ */ > > >+static inline void rte_dma_rmb(void); > > >+ > > > #endif /* __DOXYGEN__ */ > > > /** > > > > I'm not an ARMv8 expert so, my comments could be a bit ignorant. > > I'd like to understand the difference between io and added here dma > > barriers. > > The difference should be clearly explained. Otherwise we'll constantly hit > > on incorrect choice of barrier type. > > Also I don't understand why "dma" name is chosen taking into account > > that definition is bound to coherent memory between lcore and IO device. > > A good explanation can be found here. > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1077fa36f23e259858caf6f269a47393a5aff523 I agree that something more is needed to explain when to use rte_io_*. The only difference between rte_io_* and rte_dma_* is "on coherent memory".