Re: Re: [PATCH v3 1/4] config/riscv: detect V extension

[孙越池 <sunyuechi@iscas.ac.cn>]

> Please could you add a cross file in config/riscv/ for rv64gcv
> and use it in devtools/test-meson-builds.sh so we can test compiling
> with the vector extension?

Sure, I plan to submit this next week.

> Another question about RISC-V maintenance in general,
> what do you think about other pending patches for RISC-V?

I would like to prioritize merging the hwprobe detection. The related work is already mostly done here:

[PATCH v3 0/9] riscv: implement accelerated crc using zbc

The next step is to contact the author for a rebase and then review it. After that, the following patch will be handled:

[PATCH 0/2] eal/riscv: implement prefetch using zicbop

In addition, our team has several riscv v extension optimization patches that we are refining and will submit soon.

I would prefer to be added as a maintainer, as this might make communication with other authors more efficient.


> -----原始邮件-----
&gt; 发件人: "Thomas Monjalon" <thomas@monjalon.net>
&gt; 发送时间: 2025-09-20 02:16:22 (星期六)
&gt; 收件人: "Sun Yuechi" <sunyuechi@iscas.ac.cn>, uk7b@foxmail.com
&gt; 抄送: dev@dpdk.org, "Stanislaw Kardach" <stanislaw.kardach@gmail.com>, "Bruce Richardson" <bruce.richardson@intel.com>
&gt; 主题: Re: [PATCH v3 1/4] config/riscv: detect V extension
&gt; 
&gt; 19/09/2025 18:33, uk7b@foxmail.com:
&gt; &gt; From: Sun Yuechi <sunyuechi@iscas.ac.cn>
&gt; &gt; 
&gt; &gt; This patch is derived from "config/riscv: detect presence of Zbc
&gt; &gt; extension with modifications".
&gt; &gt; 
&gt; &gt; The RISC-V C api defines architecture extension test macros
&gt; &gt; These let us detect whether the V extension is supported on the
&gt; &gt; compiler and -march we're building with. The C api also defines V
&gt; &gt; intrinsics we can use rather than inline assembly on newer versions of
&gt; &gt; GCC (14.1.0+) and Clang (18.1.0+).
&gt; &gt; 
&gt; &gt; If the V extension and intrinsics are both present and we can detect
&gt; &gt; the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
&gt; &gt; 
&gt; &gt; Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
&gt; 
&gt; Series merged with style improvements, thanks.
&gt; 
&gt; Please could you add a cross file in config/riscv/ for rv64gcv
&gt; and use it in devtools/test-meson-builds.sh so we can test compiling
&gt; with the vector extension?
&gt; 
&gt; Another question about RISC-V maintenance in general,
&gt; what do you think about other pending patches for RISC-V?
&gt; 
</sunyuechi@iscas.ac.cn></sunyuechi@iscas.ac.cn></bruce.richardson@intel.com></stanislaw.kardach@gmail.com></sunyuechi@iscas.ac.cn></thomas@monjalon.net>