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Wed, 17 Apr 2019 16:28:15 +0000 From: Yongseok Koh To: Honnappa Nagarahalli CC: "jerinj@marvell.com" , "bruce.richardson@intel.com" , Pavan Nikhilesh Bhagavatula , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "Gavin Hu (Arm Technology China)" , dpdk-on-arm , nd Thread-Topic: [EXT] [PATCH 5/6] build: add option for armv8 crypto extension Thread-Index: AQHU8cm5b8SJPn5CW0moCR+0z+ooT6Y9krUAgAAZAACAAuXVEw== Date: Wed, 17 Apr 2019 16:28:15 +0000 Message-ID: <3ACFB177-32B1-4AF9-BC60-DE1EBB4EC9C7@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-6-yskoh@mellanox.com> <8328F59C-14DF-412E-A8F7-6AA1F5061065@mellanox.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b990a1f9-7d39-4012-7ddf-08d6c351b198 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SRVR:DB3PR0502MB3980; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: OBV3cJNMjnh/028dpJWYPS90mAo3NkwkjgpSMaDpLnQTXMU5Pd5u/H/Bx5cors5th4ul1SXuN0qd2g/FSBzXN/mkFDl3tbEpD1R5Qh7JNqC5sGu2aXYti0QuQs4v8caxrWDp9elxPMXaznTI9WFbkKg5vbv0PojjCXvCEK9rUeNAu20NLryNTEtXGaw/dbJYDwIlnUMjV5HW5kkkbUq1IihMHcPBxE8hXiwpnvGBVIHFeLrU6uGklE8v69iWRSscDCYnoPfucf1uETZE9EHbjRpSEMiymOYx+dQBBBuD48TjDI4seNGAyrEPCTlgylNtlMQTokLkhH/fU5SfVrQyxUu1Uu2oetEsSR7rjrJPykHFaGH0yJ8kV0IOVywkypQjgSYpxPIYrFXbQoGQ39nt9T/tPO73vqjjyDwJg+RvdoA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: b990a1f9-7d39-4012-7ddf-08d6c351b198 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2019 16:28:15.6870 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3980 Subject: Re: [dpdk-dev] [EXT] [PATCH 5/6] build: add option for armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Apr 2019 16:28:17 -0000 On Apr 15, 2019, at 1:13 PM, Honnappa Nagarahalli wrote: >>>> Subject: [EXT] [PATCH 5/6] build: add option for armv8 crypto >>>> extension >>>>=20 >>>> CONFIG_RTE_MACHINE=3D"armv8a" >>>> +CONFIG_RTE_ENABLE_ARMV8_CRYPTO=3Dy >>>=20 >>> This approach is not scalable. Even, it is not good for BlueField as >>> you you need to maintain two images. >>>=20 >>> Unlike other CPU flags, arm64's crypto cpu flag is really _optional_. >>> Access to crypto instructions is always at under runtime check. >>> See the following in rte_armv8_pmd.c >>>=20 >>>=20 >>> /* Check CPU for support for AES instruction set */ >>> if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) { >>> ARMV8_CRYPTO_LOG_ERR( >>> "AES instructions not supported by CPU"); >>> return -EFAULT; >>> } >>>=20 >>> /* Check CPU for support for SHA instruction set */ >>> if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA1) || >>> !rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA2)) { >>> ARMV8_CRYPTO_LOG_ERR( >>> "SHA1/SHA2 instructions not supported by CPU"); >>> return -EFAULT; >>> } >>>=20 >>> So In order to avoid one more config flags specific to armv8 in meson >>> and makefile build infra And avoid the need for 6/6 patch. IMO, # >>> Introduce optional CPU flag scheme in eal. Treat armv8 crypto as >>> optional flag # Skip the eal init check for optional flag. >>>=20 >>> Do you see any issues with that approach? >>=20 >> I also thought about that approach and that was my number 1 priority. >> But, I had one question came to my mind. Maybe, arm people can confirm >> it. Is it 100% guaranteed that compiler never makes use of any of crypto >> instructions even if there's no specific asm/intrinsic code? The crypto >> extension has aes, pmull, >> sha1 and sha2. In case of rte_memcpy() for x86, for example, compiler ma= y >> optimize code using avx512f instructions even though it is written >> specifically with avx2 intrinsics (__mm256_*) unless avx512f is disabled= . >>=20 >> If a complier expert in arm (or anyone else) confirm it is completely >> **optional**, then I'd love to take that approach for sure. >>=20 >> Copied dpdk-on-arm ML. >>=20 > I do not know the answer, will have to check with the compiler team. I wi= ll get back on this. Any update yet? Thanks=20 Yongseok = From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id C6261A00E6 for ; Wed, 17 Apr 2019 18:28:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E28F81B75F; Wed, 17 Apr 2019 18:28:18 +0200 (CEST) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150074.outbound.protection.outlook.com [40.107.15.74]) by dpdk.org (Postfix) with ESMTP id B36231B743 for ; Wed, 17 Apr 2019 18:28:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UtSxVLPrESvpve6b/Fb0copqQTO+8DMDDC58hXvqzTA=; b=S7jSZcLA7egJsuVkyc7TiKcRDbaSzDTabIJqMWbjoha7a1fGSYjo3YYatLQOktlNUD5mRw90kyGKiCTHD1kCEeEStPmTPVyGhcEWS/lco8jTFjwoJ3+BsXbJcIOGJiiLHfVa6SHB6vrPJIj7v59P/kJkJyi4Xb1x7DglY6U4FsQ= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1813.11; Wed, 17 Apr 2019 16:28:15 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1813.011; Wed, 17 Apr 2019 16:28:15 +0000 From: Yongseok Koh To: Honnappa Nagarahalli CC: "jerinj@marvell.com" , "bruce.richardson@intel.com" , Pavan Nikhilesh Bhagavatula , Shahaf Shuler , "dev@dpdk.org" , Thomas Monjalon , "Gavin Hu (Arm Technology China)" , dpdk-on-arm , nd Thread-Topic: [EXT] [PATCH 5/6] build: add option for armv8 crypto extension Thread-Index: AQHU8cm5b8SJPn5CW0moCR+0z+ooT6Y9krUAgAAZAACAAuXVEw== Date: Wed, 17 Apr 2019 16:28:15 +0000 Message-ID: <3ACFB177-32B1-4AF9-BC60-DE1EBB4EC9C7@mellanox.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-6-yskoh@mellanox.com> <8328F59C-14DF-412E-A8F7-6AA1F5061065@mellanox.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3980; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: OBV3cJNMjnh/028dpJWYPS90mAo3NkwkjgpSMaDpLnQTXMU5Pd5u/H/Bx5cors5th4ul1SXuN0qd2g/FSBzXN/mkFDl3tbEpD1R5Qh7JNqC5sGu2aXYti0QuQs4v8caxrWDp9elxPMXaznTI9WFbkKg5vbv0PojjCXvCEK9rUeNAu20NLryNTEtXGaw/dbJYDwIlnUMjV5HW5kkkbUq1IihMHcPBxE8hXiwpnvGBVIHFeLrU6uGklE8v69iWRSscDCYnoPfucf1uETZE9EHbjRpSEMiymOYx+dQBBBuD48TjDI4seNGAyrEPCTlgylNtlMQTokLkhH/fU5SfVrQyxUu1Uu2oetEsSR7rjrJPykHFaGH0yJ8kV0IOVywkypQjgSYpxPIYrFXbQoGQ39nt9T/tPO73vqjjyDwJg+RvdoA= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: b990a1f9-7d39-4012-7ddf-08d6c351b198 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2019 16:28:15.6870 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3980 Subject: Re: [dpdk-dev] [EXT] [PATCH 5/6] build: add option for armv8 crypto extension X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190417162815.7KEf4KkFp-ip2aaz1iQO97kosN-Oli7WmthY_T7wp28@z> On Apr 15, 2019, at 1:13 PM, Honnappa Nagarahalli wrote: >>>> Subject: [EXT] [PATCH 5/6] build: add option for armv8 crypto >>>> extension >>>>=20 >>>> CONFIG_RTE_MACHINE=3D"armv8a" >>>> +CONFIG_RTE_ENABLE_ARMV8_CRYPTO=3Dy >>>=20 >>> This approach is not scalable. Even, it is not good for BlueField as >>> you you need to maintain two images. >>>=20 >>> Unlike other CPU flags, arm64's crypto cpu flag is really _optional_. >>> Access to crypto instructions is always at under runtime check. >>> See the following in rte_armv8_pmd.c >>>=20 >>>=20 >>> /* Check CPU for support for AES instruction set */ >>> if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) { >>> ARMV8_CRYPTO_LOG_ERR( >>> "AES instructions not supported by CPU"); >>> return -EFAULT; >>> } >>>=20 >>> /* Check CPU for support for SHA instruction set */ >>> if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA1) || >>> !rte_cpu_get_flag_enabled(RTE_CPUFLAG_SHA2)) { >>> ARMV8_CRYPTO_LOG_ERR( >>> "SHA1/SHA2 instructions not supported by CPU"); >>> return -EFAULT; >>> } >>>=20 >>> So In order to avoid one more config flags specific to armv8 in meson >>> and makefile build infra And avoid the need for 6/6 patch. IMO, # >>> Introduce optional CPU flag scheme in eal. Treat armv8 crypto as >>> optional flag # Skip the eal init check for optional flag. >>>=20 >>> Do you see any issues with that approach? >>=20 >> I also thought about that approach and that was my number 1 priority. >> But, I had one question came to my mind. Maybe, arm people can confirm >> it. Is it 100% guaranteed that compiler never makes use of any of crypto >> instructions even if there's no specific asm/intrinsic code? The crypto >> extension has aes, pmull, >> sha1 and sha2. In case of rte_memcpy() for x86, for example, compiler ma= y >> optimize code using avx512f instructions even though it is written >> specifically with avx2 intrinsics (__mm256_*) unless avx512f is disabled= . >>=20 >> If a complier expert in arm (or anyone else) confirm it is completely >> **optional**, then I'd love to take that approach for sure. >>=20 >> Copied dpdk-on-arm ML. >>=20 > I do not know the answer, will have to check with the compiler team. I wi= ll get back on this. Any update yet? Thanks=20 Yongseok =