From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05D61458CD; Mon, 2 Sep 2024 11:57:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7568340B98; Mon, 2 Sep 2024 11:55:39 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by mails.dpdk.org (Postfix) with ESMTP id 0211C40668 for ; Mon, 2 Sep 2024 11:55:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725270918; x=1756806918; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nd6HdoKpZtRlzW6HL2Yt81Ib7Rn2dMgNGDVCez8GLII=; b=kGmV4eCQcFW9xJiJTlpydnEJS/ULp5bMbvk7lmgBlOjtduvEKJEiDoy7 14sm48E/sRyxpofcUTk1NVH0J9T7g8LHg0fsckLndahWL/EUSmfblnYA7 EUkAV6oyc2G0y4tMGTS6DQ4YhweNPBG4yq6zxFjKr0oxzsYnJht2N3Vzj TimdBMtg3Xp6mCALnmYYE7Cb8l68ZORd0QoWCtqRnAf9osRvRSMDHUWet QIJWDNtM+SbE1lOctpyRFBuCnJRfiJ8GjB3Sw/moLLWqLIpbAaiKIGZcJ Vl8iShNPBtOHj5gGdP+/qZd4KfQuLgii3xeFQVYyvMrd4tbwsMAGIu7Pc w==; X-CSE-ConnectionGUID: RxDAXUMZRk2d9EHo5JnAuw== X-CSE-MsgGUID: fDWQNjleRHqQeaODvgUtmA== X-IronPort-AV: E=McAfee;i="6700,10204,11182"; a="26747230" X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="26747230" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2024 02:55:17 -0700 X-CSE-ConnectionGUID: tqAVy+c3ScKXfTe0mi1Vfg== X-CSE-MsgGUID: 9TkFNMGaRlSCMrB8mKzktg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,195,1719903600"; d="scan'208";a="64597950" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by fmviesa009.fm.intel.com with ESMTP; 02 Sep 2024 02:55:16 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: bruce.richardson@intel.com Subject: [PATCH v1 19/30] net/i40e/base: align registers to the specification Date: Mon, 2 Sep 2024 10:54:31 +0100 Message-ID: <3bcfe533ee6dfe3b5f05ed6da0c897188d97e9a3.1725270827.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michal Nowak The I40E_PFPM_APM, I40E_PFPM_WUC, I40E_PFPM_WUFC, and I40E_PFPM_WUS should read bits per PF. Signed-off-by: Michal Nowak Signed-off-by: Anatoly Burakov --- drivers/net/i40e/base/i40e_register.h | 8 ++++---- drivers/net/i40e/i40e_regs.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h index 55f671c3c5..f440f0cbd1 100644 --- a/drivers/net/i40e/base/i40e_register.h +++ b/drivers/net/i40e/base/i40e_register.h @@ -3072,17 +3072,17 @@ #define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT) #define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16 #define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT) -#define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ +#define I40E_PFPM_APM(_PF) (0x000B8080 + ((_PF) * 4)) /* Reset: POR */ #define I40E_PFPM_APM_APME_SHIFT 0 #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) #define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */ #define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7 #define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0 #define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT) -#define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */ +#define I40E_PFPM_WUC(_PF) (0x0006B200 + ((_PF) * 4)) /* Reset: POR */ #define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5 #define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT) -#define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ +#define I40E_PFPM_WUFC(_PF) (0x0006B400 + ((_PF) * 4)) /* Reset: POR */ #define I40E_PFPM_WUFC_LNKC_SHIFT 0 #define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT) #define I40E_PFPM_WUFC_MAG_SHIFT 1 @@ -3123,7 +3123,7 @@ #define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT) #define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31 #define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT) -#define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */ +#define I40E_PFPM_WUS(_PF) (0x0006B600 + ((_PF) * 4)) /* Reset: POR */ #define I40E_PFPM_WUS_LNKC_SHIFT 0 #define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT) #define I40E_PFPM_WUS_MAG_SHIFT 1 diff --git a/drivers/net/i40e/i40e_regs.h b/drivers/net/i40e/i40e_regs.h index e6f8866e9f..35ff12f1f7 100644 --- a/drivers/net/i40e/i40e_regs.h +++ b/drivers/net/i40e/i40e_regs.h @@ -339,9 +339,9 @@ static const struct i40e_reg_info i40e_regs_others[] = { {I40E_GLLAN_TSOMSK_L, 0, 0, 0, 0, "GLLAN_TSOMSK_L"}, {I40E_GL_RDPU_CNTRL, 0, 0, 0, 0, "GL_RDPU_CNTRL"}, {I40E_PFPM_FHFT_LENGTH(0), 7, 128, 0, 0, "PFPM_FHFT_LENGTH"}, - {I40E_PFPM_WUC, 0, 0, 0, 0, "PFPM_WUC"}, - {I40E_PFPM_WUFC, 0, 0, 0, 0, "PFPM_WUFC"}, - {I40E_PFPM_WUS, 0, 0, 0, 0, "PFPM_WUS"}, + {I40E_PFPM_WUC(0), 0, 0, 0, 0, "PFPM_WUC"}, + {I40E_PFPM_WUFC(0), 0, 0, 0, 0, "PFPM_WUFC"}, + {I40E_PFPM_WUS(0), 0, 0, 0, 0, "PFPM_WUS"}, {I40E_PRTPM_FHFHR, 0, 0, 0, 0, "PRTPM_FHFHR"}, {I40E_GLPM_WUMC, 0, 0, 0, 0, "GLPM_WUMC"}, {I40E_VPLAN_QTABLE(0, 0), 15, 1024, 127, 4, "VPLAN_QTABLE"}, @@ -524,7 +524,7 @@ static const struct i40e_reg_info i40e_regs_others[] = { {I40E_MNGSB_WDATA, 0, 0, 0, 0, "MNGSB_WDATA"}, {I40E_MNGSB_RHDR0, 0, 0, 0, 0, "MNGSB_RHDR0"}, {I40E_MNGSB_RDATA, 0, 0, 0, 0, "MNGSB_RDATA"}, - {I40E_PFPM_APM, 0, 0, 0, 0, "PFPM_APM"}, + {I40E_PFPM_APM(0), 0, 0, 0, 0, "PFPM_APM"}, {I40E_PRTGEN_STATUS, 0, 0, 0, 0, "PRTGEN_STATUS"}, {I40E_PRTGEN_CNF, 0, 0, 0, 0, "PRTGEN_CNF"}, {I40E_PRTPM_GC, 0, 0, 0, 0, "PRTPM_GC"}, -- 2.43.5