From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F156FA09EF; Wed, 16 Dec 2020 01:55:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 44DD8C99C; Wed, 16 Dec 2020 01:55:36 +0100 (CET) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 49984C982 for ; Wed, 16 Dec 2020 01:55:35 +0100 (CET) IronPort-SDR: 3Lwkwns06NqzJT31ufPrUZRTfd3UIbJIB2rHRo3oh7Voautog0FMOmwN6pqIMjwDLQLNIKcvjv pqENcZuUCyXA== X-IronPort-AV: E=McAfee;i="6000,8403,9836"; a="236558221" X-IronPort-AV: E=Sophos;i="5.78,423,1599548400"; d="scan'208";a="236558221" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2020 16:55:33 -0800 IronPort-SDR: GzvoE6votw+mpx3/RC1BVDJf3AdHBhXRgT8vqmZNZ/InemKbpssKtEQiju0WDmX//hYn5zaupP ISOswA+6cJmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,423,1599548400"; d="scan'208";a="352183350" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga002.jf.intel.com with ESMTP; 15 Dec 2020 16:55:32 -0800 Received: from shsmsx602.ccr.corp.intel.com (10.109.6.142) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 15 Dec 2020 16:55:31 -0800 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by SHSMSX602.ccr.corp.intel.com (10.109.6.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 16 Dec 2020 08:55:30 +0800 Received: from shsmsx603.ccr.corp.intel.com ([10.109.6.143]) by SHSMSX603.ccr.corp.intel.com ([10.109.6.143]) with mapi id 15.01.1713.004; Wed, 16 Dec 2020 08:55:30 +0800 From: "Yu, DapengX" To: "Guo, Jia" CC: "dev@dpdk.org" , "Zhang, Qi Z" Thread-Topic: [PATCH] net/ixgbe: fix fdirctrl register setting Thread-Index: AQHWz13mpP3tE8eE/kuNv49W7U9EG6n3EvGAgAHZ6ZA= Date: Wed, 16 Dec 2020 00:55:29 +0000 Message-ID: <3c9b3fa64b774e2a9a6495a8346ea1dd@intel.com> References: <20201211013506.49885-1-dapengx.yu@intel.com> <07e98f22a664460c9d3180119d034e28@intel.com> In-Reply-To: <07e98f22a664460c9d3180119d034e28@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix fdirctrl register setting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jia, Thanks for your comments! Patch v2 has been sent, all your comments have specified answer in patch v2= . -----Original Message----- From: Guo, Jia=20 Sent: Tuesday, December 15, 2020 12:37 PM To: Yu, DapengX Cc: dev@dpdk.org; Yu, DapengX ; Zhang, Qi Z Subject: RE: [PATCH] net/ixgbe: fix fdirctrl register setting Hi, dapeng > -----Original Message----- > From: dapengx.yu@intel.com > Sent: Friday, December 11, 2020 9:35 AM > To: Guo, Jia > Cc: dev@dpdk.org; Yu, DapengX ; Zhang, Qi Z=20 > > Subject: [PATCH] net/ixgbe: fix fdirctrl register setting >=20 > From: YU DAPENG >=20 > The function ixgbe_fdir_set_flexbytes_offset is used when create FDir=20 > rule for flexbytes. It set a register: FDIRCTRL.FLEX_OFFSET, which=20 > cause that even if the FDir flexbytes rule is destroyed, the rule=20 > still direct the packet and transfer it to the wrong place. It is=20 > because Setting FDIRCTRL shall only be permitted on Flow Director=20 > initialization flow or Clearing the Flow Director table, otherwise=20 > unexpected happens. In order to evade the limit, add code to make setting= FDIRCTRL work without unexpected effects. >=20 > Fixes: f35fec63dde1 ("net/ixgbe: enable flex bytes for generic flow=20 > API") > Cc: qi.z.zhang@intel.com >=20 > Signed-off-by: YU DAPENG > --- > drivers/net/ixgbe/ixgbe_fdir.c | 23 +++++++++++++++++++++++=20 > drivers/net/ixgbe/ixgbe_flow.c | 7 +++---- > 2 files changed, 26 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_fdir.c=20 > b/drivers/net/ixgbe/ixgbe_fdir.c index a0fab5070..56dddd56b 100644 > --- a/drivers/net/ixgbe/ixgbe_fdir.c > +++ b/drivers/net/ixgbe/ixgbe_fdir.c > @@ -503,9 +503,32 @@ ixgbe_fdir_set_flexbytes_offset(struct=20 > rte_eth_dev *dev, > uint16_t offset) > { > struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + struct ixgbe_hw_fdir_info *fdir_info =3D > + IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data- > >dev_private); > uint32_t fdirctrl; > int i; >=20 > + if (fdir_info->flex_bytes_offset =3D=3D offset) > + return 0; > + > + fdir_info->flex_bytes_offset =3D offset; Should this value assign at the end of the polling checking? And could you kindly help to check is the timeout checking (i >=3D IXGBE_FD= IR_INIT_DONE_POLL) also need in the "ixgbe_fdir_set_flexbytes_offset"? > + > + /* /* -> /** > + * 82599 adapters flow director init flow cannot be restarted, > + * Workaround 82599 silicon errata by performing the following steps > + * before re-writing the FDIRCTRL control register with the same > value. > + * - write 1 to bit 8 of FDIRCMD register & > + * - write 0 to bit 8 of FDIRCMD register > + */ > + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, > + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | > + IXGBE_FDIRCMD_CLEARHT)); > + IXGBE_WRITE_FLUSH(hw); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, > + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & > + ~IXGBE_FDIRCMD_CLEARHT)); > + IXGBE_WRITE_FLUSH(hw); > + So you mean the above steps should be done before re-writing the FDIRCTRL, = just like the Flow Director initialization flow or Clearing the Flow Direct= or, right? If so, please refine your commit log and make it more clear, since Setting = FDIRCTRL shall is not only be permitted on Flow Director initialization flo= w or Clearing the Flow Director table. > fdirctrl =3D IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); >=20 > fdirctrl &=3D ~IXGBE_FDIRCTRL_FLEX_MASK; diff --git=20 > a/drivers/net/ixgbe/ixgbe_flow.c b/drivers/net/ixgbe/ixgbe_flow.c=20 > index 39f6ed73f..b37541d9b 100644 > --- a/drivers/net/ixgbe/ixgbe_flow.c > +++ b/drivers/net/ixgbe/ixgbe_flow.c > @@ -3137,8 +3137,6 @@ ixgbe_flow_create(struct rte_eth_dev *dev, > rte_memcpy(&fdir_info->mask, > &fdir_rule.mask, > sizeof(struct ixgbe_hw_fdir_mask)); > - fdir_info->flex_bytes_offset =3D > - fdir_rule.flex_bytes_offset; >=20 > if (fdir_rule.mask.flex_bytes_mask) > ixgbe_fdir_set_flexbytes_offset(dev, > @@ -3161,8 +3159,9 @@ ixgbe_flow_create(struct rte_eth_dev *dev, > if (ret) > goto out; >=20 > - if (fdir_info->flex_bytes_offset !=3D > - fdir_rule.flex_bytes_offset) > + if (fdir_rule.mask.flex_bytes_mask && > + (fdir_info->flex_bytes_offset !=3D Suggest you check the line align.=20 > + fdir_rule.flex_bytes_offset)) This line is the same as above. > goto out; > } > } > -- > 2.26.2.windows.1