From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 87456A052E; Mon, 9 Mar 2020 10:13:49 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A41C71BFF6; Mon, 9 Mar 2020 10:13:48 +0100 (CET) Received: from huawei.com (szxga08-in.huawei.com [45.249.212.255]) by dpdk.org (Postfix) with ESMTP id B8BF61BFF5 for ; Mon, 9 Mar 2020 10:13:47 +0100 (CET) Received: from DGGEML404-HUB.china.huawei.com (unknown [172.30.72.56]) by Forcepoint Email with ESMTP id 2AE628BCDBE26EE42C5F; Mon, 9 Mar 2020 17:13:45 +0800 (CST) Received: from DGGEML502-MBX.china.huawei.com ([169.254.2.18]) by DGGEML404-HUB.china.huawei.com ([fe80::b177:a243:7a69:5ab8%31]) with mapi id 14.03.0439.000; Mon, 9 Mar 2020 17:13:39 +0800 From: Linhaifeng To: "dev@dpdk.org" CC: "thomas@monjalon.net" , "Lilijun (Jerry)" , chenchanghu , xudingke Thread-Topic: [PATCH] cycles: add isb before read cntvct_el0 Thread-Index: AdX18vHmOeLrSwBkTbKQnNcIK5nJ0Q== Date: Mon, 9 Mar 2020 09:13:38 +0000 Message-ID: <4099DE2E54AFAD489356C6C9161D53339729EB7E@DGGEML502-MBX.china.huawei.com> Accept-Language: en-GB, zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.133.215.248] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" We nead isb rather than dsb to sync system counter to cntvct_el0. Signed-off-by: Haifeng Lin --- lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/l= ibrte_eal/common/include/arch/arm/rte_atomic_64.h index 859ae129d..705351394 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h @@ -21,6 +21,7 @@ extern "C" { =20 #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define dmb(opt) asm volatile("dmb " #opt : : : "memory") +#define isb() asm volatile("isb" : : : "memory") =20 #define rte_mb() dsb(sy) =20 @@ -186,6 +187,8 @@ rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int12= 8_t *exp, return (old.int128 =3D=3D expected.int128); } =20 +#define rte_isb() isb() + #ifdef __cplusplus } #endif diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/l= ibrte_eal/common/include/arch/arm/rte_cycles_64.h index 68e7c7338..29f524901 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h @@ -18,6 +18,7 @@ extern "C" { * The time base for this lcore. */ #ifndef RTE_ARM_EAL_RDTSC_USE_PMU + /** * This call is portable to any ARMv8 architecture, however, typically * cntvct_el0 runs at <=3D 100MHz and it may be imprecise for some tasks. @@ -27,6 +28,7 @@ rte_rdtsc(void) { uint64_t tsc; =20 + rte_isb(); asm volatile("mrs %0, cntvct_el0" : "=3Dr" (tsc)); return tsc; } --=20 2.24.1.windows.2