From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E1B3A052E; Mon, 9 Mar 2020 10:22:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 95E101C037; Mon, 9 Mar 2020 10:22:58 +0100 (CET) Received: from huawei.com (szxga03-in.huawei.com [45.249.212.189]) by dpdk.org (Postfix) with ESMTP id B60A51C036 for ; Mon, 9 Mar 2020 10:22:56 +0100 (CET) Received: from DGGEML402-HUB.china.huawei.com (unknown [172.30.72.54]) by Forcepoint Email with ESMTP id EECDD14A900E3D444B86; Mon, 9 Mar 2020 17:22:51 +0800 (CST) Received: from DGGEML421-HUB.china.huawei.com (10.1.199.38) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 9 Mar 2020 17:22:51 +0800 Received: from DGGEML502-MBX.china.huawei.com ([169.254.2.18]) by dggeml421-hub.china.huawei.com ([10.1.199.38]) with mapi id 14.03.0439.000; Mon, 9 Mar 2020 17:22:45 +0800 From: Linhaifeng To: "dev@dpdk.org" , "thomas@monjalon.net" CC: chenchanghu , xudingke , "Lilijun (Jerry)" Thread-Topic: [PATCH] cycles: add isb before read cntvct_el0 Thread-Index: AdX19BkQPgu8OpYBSl6zJ0SzB/DVyQ== Date: Mon, 9 Mar 2020 09:22:45 +0000 Message-ID: <4099DE2E54AFAD489356C6C9161D53339729EB9A@DGGEML502-MBX.china.huawei.com> Accept-Language: en-GB, zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.133.215.248] MIME-Version: 1.0 X-CFilter-Loop: Reflected Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" We should use isb rather than dsb to sync system counter to cntvct_el0. Signed-off-by: Haifeng Lin --- lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/l= ibrte_eal/common/include/arch/arm/rte_atomic_64.h index 859ae129d..7e8049725 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h @@ -21,6 +21,7 @@ extern "C" { #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define dmb(opt) asm volatile("dmb " #opt : : : "memory") +#define isb() asm volatile("isb" : : : "memory") #define rte_mb() dsb(sy) @@ -44,6 +45,8 @@ extern "C" { #define rte_cio_rmb() dmb(oshld) +#define rte_isb() isb() + /*------------------------ 128 bit atomic operations ----------------------= ---*/ #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS) diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib/l= ibrte_eal/common/include/arch/arm/rte_cycles_64.h index 68e7c7338..29f524901 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h @@ -18,6 +18,7 @@ extern "C" { * The time base for this lcore. */ #ifndef RTE_ARM_EAL_RDTSC_USE_PMU + /** * This call is portable to any ARMv8 architecture, however, typically * cntvct_el0 runs at <=3D 100MHz and it may be imprecise for some tasks. @@ -27,6 +28,7 @@ rte_rdtsc(void) { uint64_t tsc; + rte_isb(); asm volatile("mrs %0, cntvct_el0" : "=3Dr" (tsc)); return tsc; } --