From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B8C82A0563; Tue, 10 Mar 2020 08:22:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C235A1BF96; Tue, 10 Mar 2020 08:22:36 +0100 (CET) Received: from huawei.com (szxga08-in.huawei.com [45.249.212.255]) by dpdk.org (Postfix) with ESMTP id 507A51BF7F for ; Tue, 10 Mar 2020 08:22:35 +0100 (CET) Received: from DGGEML404-HUB.china.huawei.com (unknown [172.30.72.56]) by Forcepoint Email with ESMTP id 82F9860FC91E08F606CC; Tue, 10 Mar 2020 15:22:32 +0800 (CST) Received: from DGGEML424-HUB.china.huawei.com (10.1.199.41) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 10 Mar 2020 15:22:31 +0800 Received: from DGGEML502-MBX.china.huawei.com ([169.254.2.18]) by dggeml424-hub.china.huawei.com ([10.1.199.41]) with mapi id 14.03.0439.000; Tue, 10 Mar 2020 15:22:21 +0800 From: Linhaifeng To: Gavin Hu , "dev@dpdk.org" , "thomas@monjalon.net" CC: chenchanghu , xudingke , "Lilijun (Jerry)" , Honnappa Nagarahalli , Steve Capper , nd Thread-Topic: [PATCH] cycles: add isb before read cntvct_el0 Thread-Index: AdX19BkQPgu8OpYBSl6zJ0SzB/DVyQAsjRmAAAGAeGA= Date: Tue, 10 Mar 2020 07:22:21 +0000 Message-ID: <4099DE2E54AFAD489356C6C9161D53339729F402@DGGEML502-MBX.china.huawei.com> References: <4099DE2E54AFAD489356C6C9161D53339729EB9A@DGGEML502-MBX.china.huawei.com> In-Reply-To: Accept-Language: en-GB, zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.133.215.248] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected Subject: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Gavin Hu [mailto:Gavin.Hu@arm.com] > Sent: Tuesday, March 10, 2020 3:11 PM > To: Linhaifeng ; dev@dpdk.org; > thomas@monjalon.net > Cc: chenchanghu ; xudingke > ; Lilijun (Jerry) ; Honnap= pa > Nagarahalli ; Steve Capper > ; nd > Subject: RE: [PATCH] cycles: add isb before read cntvct_el0 >=20 > Hi Haifeng, >=20 > > -----Original Message----- > > From: dev On Behalf Of Linhaifeng > > Sent: Monday, March 9, 2020 5:23 PM > > To: dev@dpdk.org; thomas@monjalon.net > > Cc: chenchanghu ; xudingke > > ; Lilijun (Jerry) > > Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 > > > > We should use isb rather than dsb to sync system counter to cntvct_el0. > > > > Signed-off-by: Haifeng Lin > > --- > > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ > > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ > > 2 files changed, 5 insertions(+) > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > index 859ae129d..7e8049725 100644 > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > @@ -21,6 +21,7 @@ extern "C" { > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define > > dmb(opt) asm volatile("dmb " #opt : : : "memory") > > +#define isb() asm volatile("isb" : : : "memory") > > #define rte_mb() dsb(sy) > > @@ -44,6 +45,8 @@ extern "C" { > > #define rte_cio_rmb() dmb(oshld) > > +#define rte_isb() isb() > > + > > /*------------------------ 128 bit atomic operations > > -------------------------*/ #if defined(__ARM_FEATURE_ATOMICS) || > > defined(RTE_ARM_FEATURE_ATOMICS) > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > index 68e7c7338..29f524901 100644 > > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > @@ -18,6 +18,7 @@ extern "C" { > > * The time base for this lcore. > > */ > > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU > > + > > /** > > * This call is portable to any ARMv8 architecture, however, typically > > * cntvct_el0 runs at <=3D 100MHz and it may be imprecise for some tas= ks. > > @@ -27,6 +28,7 @@ rte_rdtsc(void) > > { > > uint64_t tsc; > > + rte_isb(); > Good catch, could you add a link to the commit log as a reference. > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/a= rch/ar > m64/include/asm/arch_timer.h?h=3Dv5.5#n220 >=20 Ok. > > asm volatile("mrs %0, cntvct_el0" : "=3Dr" (tsc)); > In kernel, there is a call to arch_counter_enforce_ordering(cnt), maybe i= t is > also necessary. > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/a= rch/ar > m64/include/asm/arch_timer.h?h=3Dv5.5#n168 Should we add isb and arch_counter_enforce_ordering in rte_rdtsc or rte_rdt= sc_precise? > > return tsc; > > } > > --