From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9862C454EF; Tue, 25 Jun 2024 13:30:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7498843352; Tue, 25 Jun 2024 13:21:46 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id 71BE842FCD for ; Tue, 25 Jun 2024 13:18:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314303; x=1750850303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oh/9dfIbA/exNmBK1afBRPMqtQ+CX1ayDVnfSDjRN5s=; b=e13cKfgLmCgUqAy7P2zNMFi6QoQwuMMDSidFiye6Bcg7NgBepXlsH0EG hwx1O3lY6A0gfZSg+Q7eeu39nW/7RJsEWgmPzy030SWcvBHhE1W2OZTlT B/OdZn7jL9TyC+2ZSzLlzIPUPBGnNqStlO56BZgRsPUVwqVOOFd5qlws/ u9E+Qc/Sc1qMOwiW9gZTTZ4dZzYsKq+e3Nttm0JH1oxAtjSi0i87WcOTZ so6RJdJk8xbJs0QFnHt7X6nkPJGq5brHHGXBy7xS9np9CJFH4R0CVXmSH qi4mSXNGJ7rGL+UH/VN9zadIWD1BHVxJAK3S83AUEXuCUtqpl8D4Rx6AX w==; X-CSE-ConnectionGUID: id/0T249TA28kEpJ2xbznA== X-CSE-MsgGUID: 0AtoHyFFSd+S4fXyjeKwCQ== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080678" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080678" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:23 -0700 X-CSE-ConnectionGUID: H/2UpS/XTCG8cwSDsiRoqQ== X-CSE-MsgGUID: roskDOd6T7GDFLrPiaFjjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719818" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:22 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Jacob Keller , bruce.richardson@intel.com, ian.stokes@intel.com Subject: [PATCH v3 126/129] net/ice/base: rename SMA register macros to match Linux upstream Date: Tue, 25 Jun 2024 12:14:11 +0100 Message-ID: <41d1a6b20c033d33b1f1e005e075f08738037e81.1719313664.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jacob Keller The macros used to define the bits for controlling the SMA are different to what we published upstream. We don't have a strong justification to change the upstream names, so fix the out-of-tree shared code to use the names as published upstream. Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.h | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 345d343a5a..9357dfd327 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -646,6 +646,21 @@ ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) #define E830_HIGH_TX_MEMORY_BANK(slot, port) \ (E830_PRTTSYN_TXTIME_H(slot) + 0x8 * (port)) +/* E810T SMA controller pin control */ +#define ICE_SMA1_DIR_EN_E810T BIT(4) +#define ICE_SMA1_TX_EN_E810T BIT(5) +#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3) +#define ICE_SMA2_DIR_EN_E810T BIT(6) +#define ICE_SMA2_TX_EN_E810T BIT(7) + +#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \ + ICE_SMA1_TX_EN_E810T) +#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \ + ICE_SMA2_DIR_EN_E810T | \ + ICE_SMA2_TX_EN_E810T) +#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \ + ICE_SMA2_MASK_E810T) + #define ICE_SMA_MIN_BIT_E810T 3 #define ICE_SMA_MAX_BIT_E810T 7 #define ICE_PCA9575_P1_OFFSET 8 @@ -660,11 +675,6 @@ ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) /* E810T PCA9575 IO controller pin control */ #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4) -#define ICE_E810T_P1_SMA1_DIR_EN BIT(4) -#define ICE_E810T_P1_SMA1_TX_EN BIT(5) -#define ICE_E810T_P1_SMA2_UFL2_RX_DIS BIT(3) -#define ICE_E810T_P1_SMA2_DIR_EN BIT(6) -#define ICE_E810T_P1_SMA2_TX_EN BIT(7) /* 56G PHY quad register base addresses */ #define ICE_PHY0_BASE 0x092000 -- 2.43.0