From: Thomas Monjalon <thomas@monjalon.net>
To: Pradeep Satyanarayana <pradeep@us.ibm.com>
Cc: bruce.richardson@intel.com, Chao Zhu <chaozhu@linux.vnet.ibm.com>,
Dekel Peled <dekelp@mellanox.com>,
dev@dpdk.org, David Christensen <drc@ibm.com>,
honnappa.nagarahalli@arm.com, konstantin.ananyev@intel.com,
ola.liljedahl@arm.com, Ori Kam <orika@mellanox.com>,
Shahaf Shuler <shahafs@mellanox.com>,
David Wilder <wilder@us.ibm.com>,
Yongseok Koh <yskoh@mellanox.com>
Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER
Date: Fri, 22 Mar 2019 18:51:17 +0100 [thread overview]
Message-ID: <4334064.10fvSv6A2r@xps> (raw)
In-Reply-To: <OF204AC919.EF7DE1FC-ON882583C5.0054B82A-882583C5.00553665@notes.na.collabserv.com>
22/03/2019 16:30, Pradeep Satyanarayana:
> Thomas Monjalon <thomas@monjalon.net> wrote on 03/22/2019 01:49:03 AM:
> > 22/03/2019 02:40, Pradeep Satyanarayana:
> > > - rte_[rw]mb (general memory barrier) --> should be lwsync
> >
> > This is what may be discussed.
> > The assumption is that the general memory barrier should cover
> > all cases (CPU caches, SMP and I/O).
> > That's why we think it should "sync" for Power.
>
> In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw]mb
> and retain it as lwsync. Agreed?
I have no clue about what is needed for SMP barrier in Power.
As long as it works as expected, no problem.
> > > - rte_smp_[rw]mb (SMP memory barrier) -->should be lwsync
> > > - rte_io_[rw]mb (I/O memory barrier) --> should be sync
> > > - rte_cio_[rw]mb (coherent I/O memory barrier) -->should be sync
> > >
> > > lwsync is appropriate for cases where CPUs are accessing cacheable
> > > memory (i.e. Memory Coherence Required) while the sync instruction
> > > should be used in all other cases.
next prev parent reply other threads:[~2019-03-22 17:51 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-18 12:58 Dekel Peled
2019-03-18 12:58 ` Dekel Peled
2019-03-19 3:24 ` Chao Zhu
2019-03-19 3:24 ` Chao Zhu
2019-03-19 10:05 ` Dekel Peled
2019-03-19 10:05 ` Dekel Peled
2019-03-19 11:14 ` Thomas Monjalon
2019-03-19 11:14 ` Thomas Monjalon
2019-03-19 19:42 ` Shahaf Shuler
2019-03-19 19:42 ` Shahaf Shuler
2019-03-19 20:45 ` Thomas Monjalon
2019-03-19 20:45 ` Thomas Monjalon
2019-03-20 22:40 ` Pradeep Satyanarayana
2019-03-20 22:40 ` Pradeep Satyanarayana
2019-03-21 8:49 ` Shahaf Shuler
2019-03-21 8:49 ` Shahaf Shuler
2019-03-22 1:40 ` Pradeep Satyanarayana
2019-03-22 1:40 ` Pradeep Satyanarayana
2019-03-22 8:49 ` Thomas Monjalon
2019-03-22 8:49 ` Thomas Monjalon
2019-03-22 15:30 ` Pradeep Satyanarayana
2019-03-22 15:30 ` Pradeep Satyanarayana
2019-03-22 17:51 ` Thomas Monjalon [this message]
2019-03-22 17:51 ` Thomas Monjalon
2019-03-22 22:57 ` Pradeep Satyanarayana
2019-03-22 22:57 ` Pradeep Satyanarayana
2019-03-24 6:37 ` Shahaf Shuler
2019-03-24 6:37 ` Shahaf Shuler
2019-03-24 17:37 ` Pradeep Satyanarayana
2019-03-24 17:37 ` Pradeep Satyanarayana
2019-03-26 9:15 ` Dekel Peled
2019-03-26 9:15 ` Dekel Peled
2019-03-27 9:19 ` Thomas Monjalon
2019-03-27 9:19 ` Thomas Monjalon
2019-03-27 23:50 ` Pradeep Satyanarayana
2019-03-27 23:50 ` Pradeep Satyanarayana
[not found] ` <OF456B0ECC.006EF7E7-ON882583CA.00827A75-882583CA.0082F7BE@LocalDomain>
2019-03-28 17:51 ` Pradeep Satyanarayana
2019-03-28 17:51 ` Pradeep Satyanarayana
2019-03-28 17:56 ` Thomas Monjalon
2019-03-28 17:56 ` Thomas Monjalon
2019-03-28 22:50 ` [dpdk-dev] [dpdk-stable] " Thomas Monjalon
2019-03-28 22:50 ` Thomas Monjalon
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