From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id C9FE31B6F0 for ; Fri, 22 Mar 2019 18:51:23 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id D105321F59; Fri, 22 Mar 2019 13:51:22 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Fri, 22 Mar 2019 13:51:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=u5RFjkfCLMg6lMPmjY5uAgkTnkmnmpfBhUTVZou1z6g=; b=rvQIB1LfEDeq v0XMRWl6k0ntAfhj9FzVMe5oUmXyobWEqTc16T5nR+23CGoWanMa/lG4pdj8j38k ncP0XHM8MRfDMmPIbAnPLSyk8JCawr1+L/6I4KKcZz3mZ45cpdi3RueF+INMdqNW 5w6FLTLUfsCAZ/SSPWkMvwJ7sNYowTY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=u5RFjkfCLMg6lMPmjY5uAgkTnkmnmpfBhUTVZou1z 6g=; b=acTZ5wRfsTV/8mIfonQ35r65wQo5FkibogKPz6rPMQgbtmwfdj8RZsI1I yT7fhsXA/Go04CFYf+fXeTW1EY+VpIAL4JQX762soVjRfQjG7HPd3vOVaGVq52iJ PwJ6YxgKj4UgCcDY0T/u4WMUBHCIZWM4riOjxzLNAyfhz/63ZjmW+imGHaNlanvy o5OjXiYqG/Psm1s96qu+rlgkKYAfdncMhxwmVHw1PhDl724F3cW7fJkN6ZbsJh9i wWQuGw3JzzZkaCtoUIPkd1ixpKgbkJrTSd/Y1Lkwco2122hXNKpHsdsUeLJ0Z0kG eO7zUUtkGoxUAoPTJiox9xc7+t3AA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedutddrjedugddutdejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecukf hppeejjedrudefgedrvddtfedrudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhh ohhmrghssehmohhnjhgrlhhonhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id ED5ABE4981; Fri, 22 Mar 2019 13:51:19 -0400 (EDT) From: Thomas Monjalon To: Pradeep Satyanarayana Cc: bruce.richardson@intel.com, Chao Zhu , Dekel Peled , dev@dpdk.org, David Christensen , honnappa.nagarahalli@arm.com, konstantin.ananyev@intel.com, ola.liljedahl@arm.com, Ori Kam , Shahaf Shuler , David Wilder , Yongseok Koh Date: Fri, 22 Mar 2019 18:51:17 +0100 Message-ID: <4334064.10fvSv6A2r@xps> In-Reply-To: References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> <11283309.AIL3tCH6tf@xps> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Mar 2019 17:51:24 -0000 22/03/2019 16:30, Pradeep Satyanarayana: > Thomas Monjalon wrote on 03/22/2019 01:49:03 AM: > > 22/03/2019 02:40, Pradeep Satyanarayana: > > > - rte_[rw]mb (general memory barrier) --> should be lwsync > > > > This is what may be discussed. > > The assumption is that the general memory barrier should cover > > all cases (CPU caches, SMP and I/O). > > That's why we think it should "sync" for Power. > > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw]mb > and retain it as lwsync. Agreed? I have no clue about what is needed for SMP barrier in Power. As long as it works as expected, no problem. > > > - rte_smp_[rw]mb (SMP memory barrier) -->should be lwsync > > > - rte_io_[rw]mb (I/O memory barrier) --> should be sync > > > - rte_cio_[rw]mb (coherent I/O memory barrier) -->should be sync > > > > > > lwsync is appropriate for cases where CPUs are accessing cacheable > > > memory (i.e. Memory Coherence Required) while the sync instruction > > > should be used in all other cases. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 4332FA00E6 for ; Fri, 22 Mar 2019 18:51:26 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1B4981B736; Fri, 22 Mar 2019 18:51:25 +0100 (CET) Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id C9FE31B6F0 for ; Fri, 22 Mar 2019 18:51:23 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id D105321F59; Fri, 22 Mar 2019 13:51:22 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Fri, 22 Mar 2019 13:51:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=u5RFjkfCLMg6lMPmjY5uAgkTnkmnmpfBhUTVZou1z6g=; b=rvQIB1LfEDeq v0XMRWl6k0ntAfhj9FzVMe5oUmXyobWEqTc16T5nR+23CGoWanMa/lG4pdj8j38k ncP0XHM8MRfDMmPIbAnPLSyk8JCawr1+L/6I4KKcZz3mZ45cpdi3RueF+INMdqNW 5w6FLTLUfsCAZ/SSPWkMvwJ7sNYowTY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=u5RFjkfCLMg6lMPmjY5uAgkTnkmnmpfBhUTVZou1z 6g=; b=acTZ5wRfsTV/8mIfonQ35r65wQo5FkibogKPz6rPMQgbtmwfdj8RZsI1I yT7fhsXA/Go04CFYf+fXeTW1EY+VpIAL4JQX762soVjRfQjG7HPd3vOVaGVq52iJ PwJ6YxgKj4UgCcDY0T/u4WMUBHCIZWM4riOjxzLNAyfhz/63ZjmW+imGHaNlanvy o5OjXiYqG/Psm1s96qu+rlgkKYAfdncMhxwmVHw1PhDl724F3cW7fJkN6ZbsJh9i wWQuGw3JzzZkaCtoUIPkd1ixpKgbkJrTSd/Y1Lkwco2122hXNKpHsdsUeLJ0Z0kG eO7zUUtkGoxUAoPTJiox9xc7+t3AA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedutddrjedugddutdejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecukf hppeejjedrudefgedrvddtfedrudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhh ohhmrghssehmohhnjhgrlhhonhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id ED5ABE4981; Fri, 22 Mar 2019 13:51:19 -0400 (EDT) From: Thomas Monjalon To: Pradeep Satyanarayana Cc: bruce.richardson@intel.com, Chao Zhu , Dekel Peled , dev@dpdk.org, David Christensen , honnappa.nagarahalli@arm.com, konstantin.ananyev@intel.com, ola.liljedahl@arm.com, Ori Kam , Shahaf Shuler , David Wilder , Yongseok Koh Date: Fri, 22 Mar 2019 18:51:17 +0100 Message-ID: <4334064.10fvSv6A2r@xps> In-Reply-To: References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> <11283309.AIL3tCH6tf@xps> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190322175117.xAWEpECYGE23BwfJoOjPFGYvPeYq82WJYKXhs0vqyFk@z> 22/03/2019 16:30, Pradeep Satyanarayana: > Thomas Monjalon wrote on 03/22/2019 01:49:03 AM: > > 22/03/2019 02:40, Pradeep Satyanarayana: > > > - rte_[rw]mb (general memory barrier) --> should be lwsync > > > > This is what may be discussed. > > The assumption is that the general memory barrier should cover > > all cases (CPU caches, SMP and I/O). > > That's why we think it should "sync" for Power. > > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw]mb > and retain it as lwsync. Agreed? I have no clue about what is needed for SMP barrier in Power. As long as it works as expected, no problem. > > > - rte_smp_[rw]mb (SMP memory barrier) -->should be lwsync > > > - rte_io_[rw]mb (I/O memory barrier) --> should be sync > > > - rte_cio_[rw]mb (coherent I/O memory barrier) -->should be sync > > > > > > lwsync is appropriate for cases where CPUs are accessing cacheable > > > memory (i.e. Memory Coherence Required) while the sync instruction > > > should be used in all other cases.