From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F285A04B6; Thu, 17 Sep 2020 11:16:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D7E291D5C7; Thu, 17 Sep 2020 11:16:44 +0200 (CEST) Received: from mailgw01.pantheon.sk (mailgw01.pantheon.sk [46.229.239.26]) by dpdk.org (Postfix) with ESMTP id 4A8901D5C2 for ; Thu, 17 Sep 2020 11:16:43 +0200 (CEST) Received: from mailgw01.pantheon.sk (localhost.localdomain [127.0.0.1]) by mailgw01.pantheon.sk (Proxmox) with ESMTP id F26972021A3; Thu, 17 Sep 2020 11:16:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pantheon.tech; h=cc:cc:content-transfer-encoding:content-type:content-type :date:from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=dkim; bh=Uz4NP2R4rmkPaK0IB+gB B2W1d7syNDtgg7uRjR1IZCQ=; b=ukGKZLzxmTiyf+H5JrrT/kHNORt3WpMwm2Gt k6qurDSPdkYL8IALCPtWtKDZJQVDO8rQdN5JNnYjXEsWGxCzL+SuJqjhePHRFMry +otTyh2js0aCPwsLFKwgj4Jl5aE8KQfUNSqQIph2B6QKdhaHhApYA5IqiW43jmJw zbST2oaabjjAwPivw13F3aMUhi7+5XNumchpAtyWCYiX50W3t59dAZ4bunzjBjkC 7rf1iTeC8CPlZ+Bsz6L/rgRms4pMWeOxluXDhAzZxkWhLBcqIl1ifFNzW1WcTger KznWdzaP7fSDEAocZjk8ir8PFkqxqmxRt6WXiC94POxQwNLprg== From: =?iso-8859-2?Q?Juraj_Linke=B9?= To: Phil Yang , "david.marchand@redhat.com" , "dev@dpdk.org" CC: "aconole@redhat.com" , "Honnappa.Nagarahalli@arm.com" , "Ruifeng.Wang@arm.com" , "nd@arm.com" , Thomas Monjalon Thread-Topic: [dpdk-dev] [PATCH v2] test/mcslock: move performance test to perf tests Thread-Index: AQHWZI6u5rRck1fWNU+YQufv4hxux6ls3Ktg Date: Thu, 17 Sep 2020 09:16:42 +0000 Message-ID: <44517a7a02ef48fcafa893469e52ba7f@pantheon.tech> References: <1584936978-11899-1-git-send-email-phil.yang@arm.com> <1595906669-18538-1-git-send-email-phil.yang@arm.com> In-Reply-To: <1595906669-18538-1-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.101.4.10] Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] test/mcslock: move performance test to perf tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Phil Yang > Sent: Tuesday, July 28, 2020 5:24 AM > To: david.marchand@redhat.com; dev@dpdk.org > Cc: aconole@redhat.com; Honnappa.Nagarahalli@arm.com; > Ruifeng.Wang@arm.com; nd@arm.com; Thomas Monjalon > > Subject: [dpdk-dev] [PATCH v2] test/mcslock: move performance test to per= f > tests >=20 > Move the MCS lock performance test into perf tests. >=20 > Signed-off-by: Phil Yang > Reviewed-by: Gavin Hu > --- > v2: > 1. Rebase code. > 2. Split from the original patchset. >=20 > MAINTAINERS | 1 + > app/test/Makefile | 1 + > app/test/autotest_data.py | 6 +++ > app/test/meson.build | 4 +- > app/test/test_mcslock.c | 88 ------------------------------- > app/test/test_mcslock_perf.c | 121 > +++++++++++++++++++++++++++++++++++++++++++ > 6 files changed, 132 insertions(+), 89 deletions(-) create mode 100644 > app/test/test_mcslock_perf.c >=20 > diff --git a/MAINTAINERS b/MAINTAINERS > index 171c4c7..eae6034 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -265,6 +265,7 @@ MCSlock - EXPERIMENTAL > M: Phil Yang > F: lib/librte_eal/include/generic/rte_mcslock.h > F: app/test/test_mcslock.c > +F: app/test/test_mcslock_perf.c >=20 > Ticketlock > M: Joyce Kong > diff --git a/app/test/Makefile b/app/test/Makefile index f406527..e4b3327 > 100644 > --- a/app/test/Makefile > +++ b/app/test/Makefile > @@ -65,6 +65,7 @@ SRCS-y +=3D test_barrier.c SRCS-y +=3D test_malloc.c = SRCS-y > +=3D test_cycles.c SRCS-y +=3D test_mcslock.c > +SRCS-y +=3D test_mcslock_perf.c > SRCS-y +=3D test_spinlock.c > SRCS-y +=3D test_ticketlock.c > SRCS-y +=3D test_memory.c > diff --git a/app/test/autotest_data.py b/app/test/autotest_data.py index > 4b7da45..c813b93 100644 > --- a/app/test/autotest_data.py > +++ b/app/test/autotest_data.py > @@ -796,6 +796,12 @@ > "Func": default_autotest, > "Report": None, > }, > + { > + "Name": "MCS Lock performance autotest", > + "Command": "mcslock_perf_autotest", > + "Func": default_autotest, > + "Report": None, > + }, > # > # Please always make sure that ring_perf is the last test! > # > diff --git a/app/test/meson.build b/app/test/meson.build index > 786a213..59df2fd 100644 > --- a/app/test/meson.build > +++ b/app/test/meson.build > @@ -86,6 +86,7 @@ test_sources =3D files('commands.c', > 'test_meter.c', > 'test_metrics.c', > 'test_mcslock.c', > + 'test_mcslock_perf.c', > 'test_mp_secondary.c', > 'test_per_lcore.c', > 'test_pmd_perf.c', > @@ -297,7 +298,8 @@ perf_test_names =3D [ > 'hash_readwrite_perf_autotest', > 'hash_readwrite_lf_perf_autotest', > 'trace_perf_autotest', > - 'ipsec_perf_autotest', > + 'ipsec_perf_autotest', > + 'mcslock_perf_autotest', > ] >=20 > driver_test_names =3D [ > diff --git a/app/test/test_mcslock.c b/app/test/test_mcslock.c index > ddccaaf..a1dc610 100644 > --- a/app/test/test_mcslock.c > +++ b/app/test/test_mcslock.c > @@ -32,23 +32,16 @@ > * > * - The function takes the global lock, display something, then relea= ses > * the global lock on each core. > - * > - * - A load test is carried out, with all cores attempting to lock a sin= gle > - * lock multiple times. > */ >=20 > RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_me); > RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_try_me); - > RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_perf_me); >=20 > rte_mcslock_t *p_ml; > rte_mcslock_t *p_ml_try; > -rte_mcslock_t *p_ml_perf; >=20 > static unsigned int count; >=20 > -static rte_atomic32_t synchro; > - > static int > test_mcslock_per_core(__rte_unused void *arg) { @@ -63,85 +56,8 @@ > test_mcslock_per_core(__rte_unused void *arg) > return 0; > } >=20 > -static uint64_t time_count[RTE_MAX_LCORE] =3D {0}; > - > #define MAX_LOOP 1000000 >=20 > -static int > -load_loop_fn(void *func_param) > -{ > - uint64_t time_diff =3D 0, begin; > - uint64_t hz =3D rte_get_timer_hz(); > - volatile uint64_t lcount =3D 0; > - const int use_lock =3D *(int *)func_param; > - const unsigned int lcore =3D rte_lcore_id(); > - > - /**< Per core me node. */ > - rte_mcslock_t ml_perf_me =3D RTE_PER_LCORE(_ml_perf_me); > - > - /* wait synchro */ > - while (rte_atomic32_read(&synchro) =3D=3D 0) > - ; > - > - begin =3D rte_get_timer_cycles(); > - while (lcount < MAX_LOOP) { > - if (use_lock) > - rte_mcslock_lock(&p_ml_perf, &ml_perf_me); > - > - lcount++; > - if (use_lock) > - rte_mcslock_unlock(&p_ml_perf, &ml_perf_me); > - } > - time_diff =3D rte_get_timer_cycles() - begin; > - time_count[lcore] =3D time_diff * 1000000 / hz; > - return 0; > -} > - > -static int > -test_mcslock_perf(void) > -{ > - unsigned int i; > - uint64_t total =3D 0; > - int lock =3D 0; > - const unsigned int lcore =3D rte_lcore_id(); > - > - printf("\nTest with no lock on single core...\n"); > - rte_atomic32_set(&synchro, 1); > - load_loop_fn(&lock); > - printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > - lcore, time_count[lcore]); > - memset(time_count, 0, sizeof(time_count)); > - > - printf("\nTest with lock on single core...\n"); > - lock =3D 1; > - rte_atomic32_set(&synchro, 1); > - load_loop_fn(&lock); > - printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > - lcore, time_count[lcore]); > - memset(time_count, 0, sizeof(time_count)); > - > - printf("\nTest with lock on %u cores...\n", (rte_lcore_count())); > - > - rte_atomic32_set(&synchro, 0); > - rte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MASTER); > - > - /* start synchro and launch test on master */ > - rte_atomic32_set(&synchro, 1); > - load_loop_fn(&lock); > - > - rte_eal_mp_wait_lcore(); > - > - RTE_LCORE_FOREACH(i) { > - printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > - i, time_count[i]); > - total +=3D time_count[i]; > - } > - > - printf("Total Cost Time =3D %"PRIu64" us\n", total); > - > - return 0; > -} > - > /* > * Use rte_mcslock_trylock() to trylock a mcs lock object, > * If it could not lock the object successfully, it would @@ -240,10 +15= 6,6 @@ > test_mcslock(void) > ret =3D -1; > rte_mcslock_unlock(&p_ml, &ml_me); >=20 > - /* mcs lock perf test */ > - if (test_mcslock_perf() < 0) > - return -1; > - > return ret; > } >=20 > diff --git a/app/test/test_mcslock_perf.c b/app/test/test_mcslock_perf.c = new > file mode 100644 index 0000000..6948344 > --- /dev/null > +++ b/app/test/test_mcslock_perf.c > @@ -0,0 +1,121 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2019 Arm Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "test.h" > + > +/* > + * RTE MCS lock perf test > + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + * > + * These tests are derived from spin lock perf test cases. > + * > + * - A load test is carried out, with all cores attempting to lock a sin= gle > + * lock multiple times. > + */ > + > +RTE_DEFINE_PER_LCORE(rte_mcslock_t, _ml_perf_me); rte_mcslock_t > +*p_ml_perf; > + > +static rte_atomic32_t synchro; > +static uint64_t time_count[RTE_MAX_LCORE] =3D {0}; > + > +#define MAX_LOOP 1000000 > + > +static int > +load_loop_fn(void *func_param) > +{ > + uint64_t time_diff =3D 0, begin; > + uint64_t hz =3D rte_get_timer_hz(); > + volatile uint64_t lcount =3D 0; > + const int use_lock =3D *(int *)func_param; > + const unsigned int lcore =3D rte_lcore_id(); > + > + /**< Per core me node. */ > + rte_mcslock_t ml_perf_me =3D RTE_PER_LCORE(_ml_perf_me); > + > + /* wait synchro */ > + while (rte_atomic32_read(&synchro) =3D=3D 0) > + ; > + > + begin =3D rte_get_timer_cycles(); > + while (lcount < MAX_LOOP) { > + if (use_lock) > + rte_mcslock_lock(&p_ml_perf, &ml_perf_me); > + > + lcount++; > + if (use_lock) > + rte_mcslock_unlock(&p_ml_perf, &ml_perf_me); > + } > + time_diff =3D rte_get_timer_cycles() - begin; > + time_count[lcore] =3D time_diff * 1000000 / hz; > + return 0; > +} > + > +/* > + * Test rte_eal_get_lcore_state() in addition to mcs locks > + * as we have "waiting" then "running" lcores. > + */ > +static int > +test_mcslock_perf(void) > +{ > + unsigned int i; > + uint64_t total =3D 0; > + int lock =3D 0; > + const unsigned int lcore =3D rte_lcore_id(); > + > + printf("\nTest with no lock on single core...\n"); > + rte_atomic32_set(&synchro, 1); > + load_loop_fn(&lock); > + printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > + lcore, time_count[lcore]); > + memset(time_count, 0, sizeof(time_count)); > + > + printf("\nTest with lock on single core...\n"); > + lock =3D 1; > + rte_atomic32_set(&synchro, 1); > + load_loop_fn(&lock); > + printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > + lcore, time_count[lcore]); > + memset(time_count, 0, sizeof(time_count)); > + > + printf("\nTest with lock on %u cores...\n", (rte_lcore_count())); > + > + rte_atomic32_set(&synchro, 0); > + rte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MASTER); > + > + /* start synchro and launch test on master */ > + rte_atomic32_set(&synchro, 1); > + load_loop_fn(&lock); > + > + rte_eal_mp_wait_lcore(); > + > + RTE_LCORE_FOREACH(i) { > + printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > + i, time_count[i]); > + total +=3D time_count[i]; > + } > + > + printf("Total Cost Time =3D %"PRIu64" us\n", total); > + > + return 0; > +} > + > +REGISTER_TEST_COMMAND(mcslock_perf_autotest, test_mcslock_perf); > -- > 2.7.4 >=20 Reviewed-by: Juraj Linke=B9