From: sunyuechi <sunyuechi@iscas.ac.cn>
To: Qiguo Chen <chen.qiguo@zte.com.cn>,
stanislaw.kardach@gmail.com, stephen@networkplumber.org
Cc: dev@dpdk.org, bruce.richardson@intel.com
Subject: Re: [PATCH v6 1/1] eal/riscv: optimize rte_memcpy with vector and zicbop extensions
Date: Mon, 17 Nov 2025 12:19:49 +0800 [thread overview]
Message-ID: <4615b675-6847-4f3b-925f-75df52be5bcc@iscas.ac.cn> (raw)
In-Reply-To: <20251024072734.1573077-2-chen.qiguo@zte.com.cn>
> > # detect extensions
> > # Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
> > if (riscv_extension_macros and
> > (cc.get_define('__riscv_zicbop', args: machine_args) != ''))
> > if ((cc.get_id() == 'gcc' and
cc.version().version_compare('>=14.1.0'))
> > or (cc.get_id() == 'clang' and
cc.version().version_compare('>=18.1.0')))
> > message('Compiling with the zicbop extension')
> > machine_args += ['-DRTE_RISCV_FEATURE_PREFETCH']
> > else
> > warning('Detected zicbop extension but cannot use because
intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
> > endif
> > endif
>
> The implementation does not involve intrinsics
It looks like nothing has been changed here yet.
> #if defined(RTE_RISCV_FEATURE_V) &&
!(defined(RTE_RISCV_FEATURE_PREFETCH))
> #undef RTE_RISCV_FEATURE_V
> #endif
>
> static __rte_always_inline void
> _rte_mov128blocks(uint8_t *dst, const uint8_t *src, size_t n)
> {
> asm volatile (
> "prefetch.r 64(%1)\n"
> "prefetch.w 64(%0)\n"
> "prefetch.r 128(%1)\n"
> "prefetch.w 128(%0)\n"
> "prefetch.r 192(%1)\n"
> "prefetch.w 192(%0)\n"
> "prefetch.r 256(%1)\n"
> "prefetch.w 256(%0)\n"
> "prefetch.r 320(%1)\n"
> "prefetch.w 320(%0)\n"
> "prefetch.r 384(%1)\n"
> "prefetch.w 384(%0)\n"
> "prefetch.r 448(%1)\n"
> "prefetch.w 448(%0)\n"
> "prefetch.r 512(%1)\n"
> "li t6, 512\n"
> "3:\n"
> "li t5, 128;"
> "vsetvli zero, t5, e8, m8, ta, ma\n"
With the current compilation conditions, if zicbop isn’t supported, the
v-optimization also won’t be compiled.
Have you tested the performance difference if you remove these
prefetches and only use v?
Can we use a condition like this to support only v?
#if defined(RTE_RISCV_FEATURE_V)
#if (defined(RTE_RISCV_FEATURE_PREFETCH))
...
#endif
...
#endif
next prev parent reply other threads:[~2025-11-17 4:19 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 9:09 [PATCH v1 0/2] Optimization Summary for RISC-V rte_memcpy Qiguo Chen
2025-10-16 9:09 ` [PATCH v1 1/2] riscv support rte_memcpy in vector Qiguo Chen
2025-10-17 5:29 ` sunyuechi
2025-10-17 10:10 ` chen.qiguo
2025-10-17 9:36 ` [PATCH v2 0/1] Optimization Summary for RISC-V rte_memcpy Qiguo Chen
2025-10-17 9:36 ` [PATCH v2 1/1] riscv support rte_memcpy in vector Qiguo Chen
2025-10-20 9:43 ` sunyuechi
2025-10-20 12:08 ` [PATCH v3 0/1] Optimization Summary for RISC-V rte_memcpy Qiguo Chen
2025-10-20 12:08 ` [PATCH v3 1/1] lib/eal/riscv: optimize rte_memcpy with RISCV vector and zicbop extensions Qiguo Chen
2025-10-21 6:56 ` [PATCH v4 0/1] Optimization Summary for RISC-V rte_memcpy Qiguo Chen
2025-10-21 6:56 ` [PATCH v4 1/1] eal/riscv: optimize rte_memcpy with vector and zicbop extensions Qiguo Chen
2025-10-24 2:56 ` retest Qiguo Chen
2025-10-30 15:35 ` retest Stephen Hemminger
2025-10-24 3:04 ` retest Qiguo Chen
2025-10-24 3:12 ` retest Qiguo Chen
2025-10-24 5:04 ` retest Qiguo Chen
2025-10-24 5:41 ` [PATCH v5 0/1] Optimization Summary for RISC-V rte_memcpy Qiguo Chen
2025-10-24 5:41 ` [PATCH v5 1/1] eal/riscv: optimize rte_memcpy with vector and zicbop extensions Qiguo Chen
2025-10-24 7:27 ` [PATCH v6 0/1] Optimization Summary for RISC-V rte_memcpy Qiguo Chen
2025-10-24 7:27 ` [PATCH v6 1/1] eal/riscv: optimize rte_memcpy with vector and zicbop extensions Qiguo Chen
2025-11-17 4:19 ` sunyuechi [this message]
2025-11-17 9:12 ` chen.qiguo
2025-10-24 16:27 ` [PATCH v5 " Stephen Hemminger
2025-11-17 4:11 ` sunyuechi
2025-10-16 9:09 ` [PATCH v1 2/2] benchmark report for rte_memcpy Qiguo Chen
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