From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1CFDA0C43; Wed, 15 Sep 2021 04:45:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7A1694014F; Wed, 15 Sep 2021 04:45:39 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 8F9BC4003C; Wed, 15 Sep 2021 04:45:37 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10107"; a="201698487" X-IronPort-AV: E=Sophos;i="5.85,292,1624345200"; d="scan'208";a="201698487" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2021 19:45:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,292,1624345200"; d="scan'208";a="529210876" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by fmsmga004.fm.intel.com with ESMTP; 14 Sep 2021 19:45:36 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Tue, 14 Sep 2021 19:45:35 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Wed, 15 Sep 2021 10:45:33 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.012; Wed, 15 Sep 2021 10:45:33 +0800 From: "Zhang, Qi Z" To: Qiming Chen , "dev@dpdk.org" CC: "Xing, Beilei" , "Wu, Jingjing" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] net/iavf: fix rxq buf size alignment Thread-Index: AQHXprIC6cEx4HgJQUmRbdqvfQrvXaukaf2w Date: Wed, 15 Sep 2021 02:45:33 +0000 Message-ID: <47416ad823b4419b9d03cbdb6d8d7463@intel.com> References: <20210911020756.3097-1-chenqiming_huawei@163.com> In-Reply-To: <20210911020756.3097-1-chenqiming_huawei@163.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/iavf: fix rxq buf size alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Qiming Chen > Sent: Saturday, September 11, 2021 10:08 AM > To: dev@dpdk.org > Cc: Xing, Beilei ; Wu, Jingjing ; > Qiming Chen ; stable@dpdk.org > Subject: [dpdk-dev] [PATCH] net/iavf: fix rxq buf size alignment >=20 > The RTE_ALIGN macro is aligned upwards. If the buf_size variable is not a= ligned > with 1 << I40E_RXQ_CTX_DBUFF_SHIFT, the rx_buf_len is larger than the > actual mbuf memory after the operation. When receiving the packet, if the > packet is larger than the configured buf_size, it will cause a memory ste= pping > event. >=20 > The patch uses the RTE_ALIGN_FLOOR down alignment macro to correct the > problem. >=20 > Fixes: 69dd4c3d0898 ("net/avf: enable queue and device") > Cc: stable@dpdk.org >=20 > Signed-off-by: Qiming Chen Acked-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi