From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 918C2A0540; Mon, 20 Jul 2020 10:54:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3C28F1DBB; Mon, 20 Jul 2020 10:54:45 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 31FC81023 for ; Mon, 20 Jul 2020 10:54:43 +0200 (CEST) IronPort-SDR: 85xgHAGXM3JhwFZiiezLWjASJV7aIB75GwUt34iHboyEo/KQzkHsAnvRHqgludtEvf/3/+AtLQ NafEpZ3A0uRA== X-IronPort-AV: E=McAfee;i="6000,8403,9687"; a="214557367" X-IronPort-AV: E=Sophos;i="5.75,374,1589266800"; d="scan'208";a="214557367" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2020 01:54:42 -0700 IronPort-SDR: YhiNkvVYFzm8LjrnBGrNRKBE37suVr+vTGov8J0JHufhS2ZFsHJr2AHTx4YmvYAaUd3B7HwkKy dtHSix4BfbgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,374,1589266800"; d="scan'208";a="361959498" Received: from unknown (HELO [10.251.87.74]) ([10.251.87.74]) by orsmga001.jf.intel.com with ESMTP; 20 Jul 2020 01:54:39 -0700 To: Ruifeng Wang , "dev@dpdk.org" Cc: "beilei.xing@intel.com" , "jia.guo@intel.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , "jerinjacobk@gmail.com" , "david.marchand@redhat.com" , "fiona.trahe@intel.com" , "wei.zhao1@intel.com" , nd References: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> <1594982985-31551-1-git-send-email-radu.nicolau@intel.com> <1594982985-31551-3-git-send-email-radu.nicolau@intel.com> From: "Nicolau, Radu" Message-ID: <482f5554-912f-cbf7-2679-b3295929068d@intel.com> Date: Mon, 20 Jul 2020 09:54:39 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-GB Subject: Re: [dpdk-dev] [PATCH v8 2/4] net/i40e: use WC store to update queue tail registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 7/20/2020 7:46 AM, Ruifeng Wang wrote: >> -----Original Message----- >> From: Radu Nicolau >> Sent: Friday, July 17, 2020 6:50 PM >> To: dev@dpdk.org >> Cc: beilei.xing@intel.com; jia.guo@intel.com; bruce.richardson@intel.com; >> konstantin.ananyev@intel.com; jerinjacobk@gmail.com; >> david.marchand@redhat.com; fiona.trahe@intel.com; wei.zhao1@intel.com; >> Ruifeng Wang ; Radu Nicolau >> >> Subject: [PATCH v8 2/4] net/i40e: use WC store to update queue tail registers >> >> Performance improvement: use a write combining store instead of a regular >> mmio write to update queue tail registers. >> >> Signed-off-by: Radu Nicolau >> Acked-by: Bruce Richardson >> --- >> drivers/net/i40e/base/i40e_osdep.h | 5 +++++ >> drivers/net/i40e/i40e_rxtx.c | 8 ++++---- >> drivers/net/i40e/i40e_rxtx_vec_avx2.c | 4 ++-- >> drivers/net/i40e/i40e_rxtx_vec_sse.c | 4 ++-- >> 4 files changed, 13 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/net/i40e/base/i40e_osdep.h >> b/drivers/net/i40e/base/i40e_osdep.h >> index 58be396..69ab717 100644 >> --- a/drivers/net/i40e/base/i40e_osdep.h >> +++ b/drivers/net/i40e/base/i40e_osdep.h >> @@ -138,6 +138,11 @@ static inline uint32_t i40e_read_addr(volatile void >> *addr) >> #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \ >> rte_write32_relaxed((rte_cpu_to_le_32(value)), reg) >> >> +#define I40E_PCI_REG_WC_WRITE(queue, reg, value) \ > 'queue' is not necessary since it will not be used. It can be removed? Yes, I will remove it - in the first version we had a flag in the queue struct, and this macro was not properly updated. > > Thanks. > /Ruifeng >> + rte_write32_wc((rte_cpu_to_le_32(value)), reg) #define >> +I40E_PCI_REG_WC_WRITE_RELAXED(queue, reg, value) \ >> + rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg) >> + >> #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT) >> #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT) >> >> diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index >> 840b6f3..64e43ac 100644 >> --- a/drivers/net/i40e/i40e_rxtx.c >> +++ b/drivers/net/i40e/i40e_rxtx.c >> @@ -760,7 +760,7 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf >> **rx_pkts, uint16_t nb_pkts) >> if (nb_hold > rxq->rx_free_thresh) { >> rx_id = (uint16_t) ((rx_id == 0) ? >> (rxq->nb_rx_desc - 1) : (rx_id - 1)); >> - I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); >> + I40E_PCI_REG_WC_WRITE(rxq, rxq->qrx_tail, rx_id); >> nb_hold = 0; >> } >> rxq->nb_rx_hold = nb_hold; >> @@ -938,7 +938,7 @@ i40e_recv_scattered_pkts(void *rx_queue, >> if (nb_hold > rxq->rx_free_thresh) { >> rx_id = (uint16_t)(rx_id == 0 ? >> (rxq->nb_rx_desc - 1) : (rx_id - 1)); >> - I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); >> + I40E_PCI_REG_WC_WRITE(rxq, rxq->qrx_tail, rx_id); >> nb_hold = 0; >> } >> rxq->nb_rx_hold = nb_hold; >> @@ -1249,7 +1249,7 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf >> **tx_pkts, uint16_t nb_pkts) >> (unsigned) tx_id, (unsigned) nb_tx); >> >> rte_cio_wmb(); >> - I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id); >> + I40E_PCI_REG_WC_WRITE_RELAXED(txq, txq->qtx_tail, tx_id); >> txq->tx_tail = tx_id; >> >> return nb_tx; >> @@ -1400,7 +1400,7 @@ tx_xmit_pkts(struct i40e_tx_queue *txq, >> txq->tx_tail = 0; >> >> /* Update the tx tail register */ >> - I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); >> + I40E_PCI_REG_WC_WRITE(txq, txq->qtx_tail, txq->tx_tail); >> >> return nb_pkts; >> } >> diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx2.c >> b/drivers/net/i40e/i40e_rxtx_vec_avx2.c >> index 3bcef13..294c1c4 100644 >> --- a/drivers/net/i40e/i40e_rxtx_vec_avx2.c >> +++ b/drivers/net/i40e/i40e_rxtx_vec_avx2.c >> @@ -134,7 +134,7 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq) >> (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); >> >> /* Update the tail pointer on the NIC */ >> - I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); >> + I40E_PCI_REG_WC_WRITE(rxq, rxq->qrx_tail, rx_id); >> } >> >> #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC >> @@ -921,7 +921,7 @@ i40e_xmit_fixed_burst_vec_avx2(void *tx_queue, >> struct rte_mbuf **tx_pkts, >> >> txq->tx_tail = tx_id; >> >> - I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); >> + I40E_PCI_REG_WC_WRITE(txq, txq->qtx_tail, txq->tx_tail); >> >> return nb_pkts; >> } >> diff --git a/drivers/net/i40e/i40e_rxtx_vec_sse.c >> b/drivers/net/i40e/i40e_rxtx_vec_sse.c >> index 6985183..a4635e0 100644 >> --- a/drivers/net/i40e/i40e_rxtx_vec_sse.c >> +++ b/drivers/net/i40e/i40e_rxtx_vec_sse.c >> @@ -86,7 +86,7 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq) >> (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); >> >> /* Update the tail pointer on the NIC */ >> - I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); >> + I40E_PCI_REG_WC_WRITE(rxq, rxq->qrx_tail, rx_id); >> } >> >> #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC >> @@ -733,7 +733,7 @@ i40e_xmit_fixed_burst_vec(void *tx_queue, struct >> rte_mbuf **tx_pkts, >> >> txq->tx_tail = tx_id; >> >> - I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); >> + I40E_PCI_REG_WC_WRITE(txq, txq->qtx_tail, txq->tx_tail); >> >> return nb_pkts; >> } >> -- >> 2.7.4