From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id E638210BFC for ; Wed, 21 Dec 2016 11:31:37 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP; 21 Dec 2016 02:31:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,383,1477983600"; d="scan'208";a="914747479" Received: from pgsmsx108.gar.corp.intel.com ([10.221.44.103]) by orsmga003.jf.intel.com with ESMTP; 21 Dec 2016 02:31:36 -0800 Received: from pgsmsx106.gar.corp.intel.com ([169.254.9.52]) by PGSMSX108.gar.corp.intel.com ([169.254.8.244]) with mapi id 14.03.0248.002; Wed, 21 Dec 2016 18:31:35 +0800 From: "Dai, Wei" To: "Yigit, Ferruh" , "Zhang, Helin" , "Ananyev, Konstantin" CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 27/29] net/ixgbe/base: add write flush required by Inphi Thread-Index: AQHSTfiwotUCTNi7PUi841/kjS9fIKD5PNMAgBkOGHA= Date: Wed, 21 Dec 2016 10:31:34 +0000 Message-ID: <49759EB36A64CF4892C1AFEC9231E8D63A30A542@PGSMSX106.gar.corp.intel.com> References: <1480833100-48545-1-git-send-email-wei.dai@intel.com> <1480833100-48545-27-git-send-email-wei.dai@intel.com> <10604e95-4011-00d4-cc4f-42bf0feacf3d@intel.com> In-Reply-To: <10604e95-4011-00d4-cc4f-42bf0feacf3d@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiY2UzZjVmMjEtNjFjZC00OGQwLTk5ZDQtNjE0OTdjYzcxODE2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IjZBVWhLdVNxbmp5VnFTbkJBQlFLbzNodkpRUXBjZ2N3OGRpVWxLSXBVY1U9In0= x-ctpclassification: CTP_IC x-originating-ip: [172.30.20.205] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 27/29] net/ixgbe/base: add write flush required by Inphi X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Dec 2016 10:31:38 -0000 > -----Original Message----- > From: Yigit, Ferruh > Sent: Tuesday, December 6, 2016 3:41 AM > To: Dai, Wei ; Zhang, Helin ; > Ananyev, Konstantin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH 27/29] net/ixgbe/base: add write flush req= uired > by Inphi >=20 > On 12/4/2016 6:31 AM, Wei Dai wrote: > > This patch updates Inphi configuration to flush the register write > > with >=20 > Do we really need to mention from Inphi here? If so, can you please expla= in > what it is? Inphi (www.inphi.com) is a company which provides PHYs. So I will use "Inphi PHY" instead of "Inphi" in v2 patch set. >=20 > > a reg read. Inphi is configured in ixgbe_setup_mac_link_sfp_x550a. > > The Inphy setup flow has been updated to read configuration reg, write > > only linear/non-linear, and then read (write flush). >=20 > Also patch does [1] seems not mentioned in the commit log, can you please= add > information for it? Yes, following statement is redundant, but in order to simplify the process= to=20 keep up with the shared code provided by another team (Intel Network Divisi= on),=20 I'd like to keep it here. Anyway it is harmless. >=20 > [1] > > + reg_phy_ext &=3D ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | > > + (IXGBE_CS4227_EDC_MODE_SR << 1)); >=20 > > > > Signed-off-by: Wei Dai > > --- > > drivers/net/ixgbe/base/ixgbe_x550.c | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c > > b/drivers/net/ixgbe/base/ixgbe_x550.c > > index 4a98530..a57ba74 100644 > > --- a/drivers/net/ixgbe/base/ixgbe_x550.c > > +++ b/drivers/net/ixgbe/base/ixgbe_x550.c > > @@ -2834,12 +2834,26 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct > > ixgbe_hw *hw, > > > > /* Configure CS4227/CS4223 LINE side to proper mode. */ > > reg_slice =3D IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; > > + > > + ret_val =3D hw->phy.ops.read_reg(hw, reg_slice, > > + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); > > + > > + if (ret_val !=3D IXGBE_SUCCESS) > > + return ret_val; > > + > > + reg_phy_ext &=3D ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | > > + (IXGBE_CS4227_EDC_MODE_SR << 1)); > > + > > if (setup_linear) > > reg_phy_ext =3D (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; > > else > > reg_phy_ext =3D (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; > > ret_val =3D hw->phy.ops.write_reg(hw, reg_slice, > > IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); > > + > > + /* Flush previous write with a read */ > > + ret_val =3D hw->phy.ops.read_reg(hw, reg_slice, > > + IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); > > } > > return ret_val; > > } > >