From: Thomas Monjalon <thomas@monjalon.net>
To: Alexander Kozyrev <akozyrev@nvidia.com>
Cc: dev@dpdk.org, stable@dpdk.org, rasland@nvidia.com,
matan@nvidia.com, viacheslavo@nvidia.com
Subject: Re: [dpdk-dev] [PATCH v2] net/mlx5: fix meta register conversion for extensive mode
Date: Thu, 22 Jul 2021 16:25:27 +0200 [thread overview]
Message-ID: <4977419.P8Za4hhJ44@thomas> (raw)
In-Reply-To: <20210720075138.985097-1-akozyrev@nvidia.com>
20/07/2021 09:51, Alexander Kozyrev:
> Register C is used in the extensive metadata mode number 1 and its
> width can vary from 0 to 32 bits depending on the kernel usage of it.
>
> There are several issues associated with this mode (dv_xmeta_en=1):
> 1. The metadata setting assumes that the width is always 16 bits,
> which is the most common case in this mode. Use the proper mask.
> 2. The same is true for the modify_field Flow API. 16-bits width
> is hardcoded for dv_xmeta_en=1. Switch to the register C mask width.
> 3. Metadata is stored in the most significant bits in CQE in this
> mode because the registers copy code was not updated during the
> metadata conversion to the big-endian format. Update this code to
> avoid shifting the metadata in the datapath.
>
> Fixes: b57e414b48 ("net/mlx5: convert meta register to big-endian")
> Cc: stable@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Applied, thanks
prev parent reply other threads:[~2021-07-22 14:25 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 7:47 [dpdk-dev] [PATCH] " Alexander Kozyrev
2021-07-20 7:51 ` [dpdk-dev] [PATCH v2] " Alexander Kozyrev
2021-07-22 14:25 ` Thomas Monjalon [this message]
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