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Fri, 12 Apr 2019 02:04:45 +0000 From: Yongseok Koh To: Pavan Nikhilesh Bhagavatula CC: Thomas Monjalon , dev , Jerin Jacob Kollanukkaran , "jerinjacobk@gmail.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y1qMWAgADReACAAOv/AIAAYoOA Date: Fri, 12 Apr 2019 02:04:45 +0000 Message-ID: <4B4ECE0C-8554-473F-B79E-B15403F34190@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: eb004ac6-39e3-4c1b-5b46-08d6beeb3c02 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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SRVR:DB3PR0502MB3945; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: uOykmQxA64f5pgPqVWe038k1o/l1bvME3A2GfpneoEnrqPckPoVKixFAO6cQ3QrWongMNhIUZazdieGGUkQr0rXNXgqOS3FSkeqrZXbjTDvpsjzl6duLEr3jLOBlen3sZjYqZN2X1z5qk5jv7b0JcvH71bHurPHo6ARbGkmY8plPsMHnGaFYyAy0zSP/BzAzIzVwpBjBfo1uzv/PDjBXS6l/UtzzrpnHnXYrwWzQlV6gd1Xh7EaNGXUNwk6Aie+xBMETZmDRI8j1A3TmFwnwKSOTZDSE0ftsM5oCT+qiscmZJrI7uAoD8Ovesa3yAH454ir3evQmanCDdecmhfi6PodVmj5SxGouYZ/MCnN2DbTq0z6qDugZeeyFgTLAtbtmZsPJje8nbIXbKPSOzR8Z/nfv4ZJ72B7DNGnGaQ6LJkU= Content-Type: text/plain; charset="us-ascii" Content-ID: <06C5E41B85FE00438782D16CE62F2FF7@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: eb004ac6-39e3-4c1b-5b46-08d6beeb3c02 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 02:04:45.0911 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3945 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Apr 2019 02:04:47 -0000 > On Apr 11, 2019, at 1:12 PM, Yongseok Koh wrote: >=20 >>=20 >> On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula wrote: >>=20 >> Hi Yongseok, >>=20 >>> -----Original Message----- >>> From: Yongseok Koh >>> Sent: Wednesday, April 10, 2019 11:08 PM >>> To: Pavan Nikhilesh Bhagavatula >>> Cc: Thomas Monjalon ; dev ; Jerin >>> Jacob Kollanukkaran ; jerinjacobk@gmail.com >>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to suppor= t >>> machine specific flags >>>=20 >>> External Email >>>=20 >>> ---------------------------------------------------------------------- >>>=20 >>>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >>>>=20 >>>> From: Pavan Nikhilesh >>>>=20 >>>> Currently, RTE_* flags are set based on the implementer ID but there >>>> might be some micro arch specific differences from the same vendor eg. >>>> CACHE_LINESIZE. Add support to set micro arch specific flags. >>>>=20 >>>> Signed-off-by: Pavan Nikhilesh >>>> Signed-off-by: Jerin Jacob >>>> --- >>>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >>>> 1 file changed, 32 insertions(+), 24 deletions(-) >>>>=20 >>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>>> 170a4981a..24bce2b39 100644 >>>> --- a/config/arm/meson.build >>>> +++ b/config/arm/meson.build >>>> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >>>>=20 >>>> arm_force_native_march =3D false >>>>=20 >>>> -machine_args_generic =3D [ >>>> - ['default', ['-march=3Darmv8-a+crc+crypto']], >>>> - ['native', ['-march=3Dnative']], >>>> - ['0xd03', ['-mcpu=3Dcortex-a53']], >>>> - ['0xd04', ['-mcpu=3Dcortex-a35']], >>>> - ['0xd05', ['-mcpu=3Dcortex-a55']], >>>> - ['0xd07', ['-mcpu=3Dcortex-a57']], >>>> - ['0xd08', ['-mcpu=3Dcortex-a72']], >>>> - ['0xd09', ['-mcpu=3Dcortex-a73']], >>>> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >>>> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >>>> -] >>>> -machine_args_cavium =3D [ >>>> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>>> - ['native', ['-march=3Dnative']], >>>> - ['0xa1', ['-mcpu=3Dthunderxt88']], >>>> - ['0xa2', ['-mcpu=3Dthunderxt81']], >>>> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >>>> - >>>> flags_common_default =3D [ >>>> # Accelarate rte_memcpy. Be sure to run unit test >>> (memcpy_perf_autotest) >>>> # to determine the best threshold in code. Refer to notes in source >>>> file @@ -52,12 +33,10 @@ flags_generic =3D [ >>>> ['RTE_USE_C11_MEM_MODEL', true], >>>> ['RTE_CACHE_LINE_SIZE', 128]] >>>> flags_cavium =3D [ >>>> - ['RTE_MACHINE', '"thunderx"'], >>>> ['RTE_CACHE_LINE_SIZE', 128], >>>> ['RTE_MAX_NUMA_NODES', 2], >>>> ['RTE_MAX_LCORE', 96], >>>> - ['RTE_MAX_VFIO_GROUPS', 128], >>>> - ['RTE_USE_C11_MEM_MODEL', false]] >>>> + ['RTE_MAX_VFIO_GROUPS', 128]] >>>> flags_dpaa =3D [ >>>> ['RTE_MACHINE', '"dpaa"'], >>>> ['RTE_USE_C11_MEM_MODEL', true], >>>> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >>>> ['RTE_MAX_NUMA_NODES', 1], >>>> ['RTE_MAX_LCORE', 16], >>>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >>>> +flags_default_extra =3D [] >>>> +flags_thunderx_extra =3D [ >>>> + ['RTE_MACHINE', '"thunderx"'], >>>> + ['RTE_USE_C11_MEM_MODEL', false]] >>>> + >>>> +machine_args_generic =3D [ >>>> + ['default', ['-march=3Darmv8-a+crc+crypto']], >>>> + ['native', ['-march=3Dnative']], >>>> + ['0xd03', ['-mcpu=3Dcortex-a53']], >>>> + ['0xd04', ['-mcpu=3Dcortex-a35']], >>>> + ['0xd07', ['-mcpu=3Dcortex-a57']], >>>> + ['0xd08', ['-mcpu=3Dcortex-a72']], >>>> + ['0xd09', ['-mcpu=3Dcortex-a73']], >>>> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>>> + >>>> +machine_args_cavium =3D [ >>>> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>>> + ['native', ['-march=3Dnative']], >>>> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >>>> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >>>> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >>>>=20 >>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>>> machine_args_generic] @@ -157,8 +157,16 @@ else >>>> endif >>>> foreach marg: machine[2] >>>> if marg[0] =3D=3D impl_pn >>>> - foreach f: marg[1] >>>> - machine_args +=3D f >>>> + foreach flag: marg[1] >>>> + if cc.has_argument(flag) >>>> + machine_args +=3D flag >>>> + endif >>>> + endforeach >>>> + # Apply any extra machine specific flags. >>>> + foreach flag: marg.get(2, flags_default_extra) >>>> + if flag.length() > 0 >>>> + dpdk_conf.set(flag[0], flag[1]) >>>> + endif >>>=20 >>> Let me continue the discussion from v7 here. >>> Seems I wan't clear enough. >>>=20 >>> Let me take an example. If the host is thunderx2 (0xaf) and compiler is= older >>> than v7, flags_thunderx2_extra isn't set. This means, for example, >>> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >>> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you mig= ht >>> want to set it regardless of gcc version. You could skip setting -mcpu = with setting >>> the extra flags. >>>=20 >>=20 >> Thanks for the detailed explanation. >> I think since we have the check to skip mcpu flag when cc doesn't suppor= t it (cc.has_argument(flag)) >> It will be safe to remove=20 >> ` >> # Primary part number based mcpu flags are supported >> # for gcc versions > 7 >> if cc.version().version_compare( >> '<7.0') or cmd_output.length() =3D=3D 0 >> if not meson.is_cross_build() and arm_force_native_march = =3D=3D true >> impl_pn =3D 'native' >> else >> impl_pn =3D 'default' >> endif >> endif >> ` >=20 > +1 I've tested it but still have an issue with old gcc. Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either. So, it spews error due to lack of CRC feature. -march should have '+crc'. The error I got was: > ninja: Entering directory `build' > [942/1452] Compiling C object 'drivers/drivers...c@sta/net_softnic_rte_et= h_softnic_action.c.o'. > FAILED: drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_soft= nic_action.c.o > cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers -I../drivers -Idr= ivers/net/softnic -I../drivers/net/softnic -Ilib/librte_ethdev -I../lib/lib= rte_ethdev -I. -I../ -Iconfig -I../config-Ilib/librte_eal/common/include -I= ../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ili= b/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/ > common/include/arch/arm -I../lib/librte_eal/common/include/arch/arm -Ilib= /librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs = -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf= -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_ring -I../lib/li= brte_ring -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/lib > rte_meter -I../lib/librte_meter -Idrivers/bus/pci -I../drivers/bus/pci -I= ../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus= /vdev -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline = -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched -I../lib/librte_s= ched -Ilib/librte_ip_frag -I../lib/librte_ip_frag -Ilib/librte_h > ash -I../lib/librte_hash -Ilib/librte_cryptodev -I../lib/librte_cryptodev= -Ilib/librte_kni -I../lib/librte_kni -Ilib/librte_table -I../lib/librte_ta= ble -Ilib/librte_lpm -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_a= cl -pipe -D_FILE_OFFSET_BITS=3D64 -Wall -Winvalid-pch -O3 -include rte_conf= ig.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI > MENTAL_API -MD -MQ 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic= _rte_eth_softnic_action.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_softnic@sta/= net_softnic_rte_eth_softnic_action.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_= softnic@sta/net_softnic_rte_eth_softnic_action.c.o' -c ../drivers/net/softn= ic/rte_eth_softnic_action.c > {standard input}: Assembler messages: > {standard input}:14: Error: selected processor does not support `crc32cx = w3,w3,x0' > {standard input}:37: Error: selected processor does not support `crc32cx = w1,w1,x3' > {standard input}:40: Error: selected processor does not support `crc32cx = w0,w0,x2' My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red= Hat 4.8.5-28)' Thanks, Yongseok >=20 >>=20 >> The command output check can also be removed as it is handled when calli= ng the command script itself. >=20 > +1 >=20 >>=20 >> Thoughts? >>=20 >> PS. I think the safest way to set CACHELINE_SIZE is to read the cache ty= pe register[1] but sadly only few latest kernels=20 >> have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index= 0/coherency_line_size)=20 >=20 > +1 >=20 > In summary, +3. LoL >=20 > I'll also submit a patch to change the default cacheline size of cortex-a= 72 with the new flags_*_extra[] >=20 >=20 > thanks, > Yongseok From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 63410A0096 for ; Fri, 12 Apr 2019 04:04:50 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2417E4CC3; Fri, 12 Apr 2019 04:04:49 +0200 (CEST) Received: from EUR02-HE1-obe.outbound.protection.outlook.com (mail-eopbgr10052.outbound.protection.outlook.com [40.107.1.52]) by dpdk.org (Postfix) with ESMTP id 7EFA74CA9 for ; Fri, 12 Apr 2019 04:04:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=T06AKJaPH4aAvzmo3WG2kH1FXMJxEGWfSf/KOWtECwc=; b=JTH7Ka/Y7HFzPFSZZ1j1O3ygWjvz7UfYtDdjnJHc/Rh10ESilYe1jtiU20tkJzfpKVVnX9DCaBjATCpfwV2bZqj3tqgdfW2Gc9KWyLiMNbNlF19jZvwBPoeRk9w1OfPOK78MOxMFwG3b0ChLO/EVZk8IMfBzCf63Ib28pgAJIX0= Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com (52.134.72.27) by DB3PR0502MB3945.eurprd05.prod.outlook.com (52.134.65.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.16; Fri, 12 Apr 2019 02:04:45 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Fri, 12 Apr 2019 02:04:45 +0000 From: Yongseok Koh To: Pavan Nikhilesh Bhagavatula CC: Thomas Monjalon , dev , Jerin Jacob Kollanukkaran , "jerinjacobk@gmail.com" Thread-Topic: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU77iKYoDTLLI/t0C/tXnhCides6Y1qMWAgADReACAAOv/AIAAYoOA Date: Fri, 12 Apr 2019 02:04:45 +0000 Message-ID: <4B4ECE0C-8554-473F-B79E-B15403F34190@mellanox.com> References: <20190406142737.20091-1-jerinj@marvell.com> <20190410161400.9361-1-jerinj@marvell.com> <20190410161400.9361-2-jerinj@marvell.com> <6CED2209-E8A8-4141-869E-4505DC42CC58@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB3945; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: uOykmQxA64f5pgPqVWe038k1o/l1bvME3A2GfpneoEnrqPckPoVKixFAO6cQ3QrWongMNhIUZazdieGGUkQr0rXNXgqOS3FSkeqrZXbjTDvpsjzl6duLEr3jLOBlen3sZjYqZN2X1z5qk5jv7b0JcvH71bHurPHo6ARbGkmY8plPsMHnGaFYyAy0zSP/BzAzIzVwpBjBfo1uzv/PDjBXS6l/UtzzrpnHnXYrwWzQlV6gd1Xh7EaNGXUNwk6Aie+xBMETZmDRI8j1A3TmFwnwKSOTZDSE0ftsM5oCT+qiscmZJrI7uAoD8Ovesa3yAH454ir3evQmanCDdecmhfi6PodVmj5SxGouYZ/MCnN2DbTq0z6qDugZeeyFgTLAtbtmZsPJje8nbIXbKPSOzR8Z/nfv4ZJ72B7DNGnGaQ6LJkU= Content-Type: text/plain; charset="UTF-8" Content-ID: <06C5E41B85FE00438782D16CE62F2FF7@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: eb004ac6-39e3-4c1b-5b46-08d6beeb3c02 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 02:04:45.0911 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3945 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190412020445.wRV-EYzxHEv342l31M_8BWNI2bq1NbvmdE3mUI5Xrxc@z> > On Apr 11, 2019, at 1:12 PM, Yongseok Koh wrote: >=20 >>=20 >> On Apr 10, 2019, at 11:07 PM, Pavan Nikhilesh Bhagavatula wrote: >>=20 >> Hi Yongseok, >>=20 >>> -----Original Message----- >>> From: Yongseok Koh >>> Sent: Wednesday, April 10, 2019 11:08 PM >>> To: Pavan Nikhilesh Bhagavatula >>> Cc: Thomas Monjalon ; dev ; Jerin >>> Jacob Kollanukkaran ; jerinjacobk@gmail.com >>> Subject: [EXT] Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to suppor= t >>> machine specific flags >>>=20 >>> External Email >>>=20 >>> ---------------------------------------------------------------------- >>>=20 >>>> On Apr 10, 2019, at 9:13 AM, jerinjacobk@gmail.com wrote: >>>>=20 >>>> From: Pavan Nikhilesh >>>>=20 >>>> Currently, RTE_* flags are set based on the implementer ID but there >>>> might be some micro arch specific differences from the same vendor eg. >>>> CACHE_LINESIZE. Add support to set micro arch specific flags. >>>>=20 >>>> Signed-off-by: Pavan Nikhilesh >>>> Signed-off-by: Jerin Jacob >>>> --- >>>> config/arm/meson.build | 56 ++++++++++++++++++++++++------------------ >>>> 1 file changed, 32 insertions(+), 24 deletions(-) >>>>=20 >>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index >>>> 170a4981a..24bce2b39 100644 >>>> --- a/config/arm/meson.build >>>> +++ b/config/arm/meson.build >>>> @@ -7,25 +7,6 @@ march_opt =3D '-march=3D@0@'.format(machine) >>>>=20 >>>> arm_force_native_march =3D false >>>>=20 >>>> -machine_args_generic =3D [ >>>> - ['default', ['-march=3Darmv8-a+crc+crypto']], >>>> - ['native', ['-march=3Dnative']], >>>> - ['0xd03', ['-mcpu=3Dcortex-a53']], >>>> - ['0xd04', ['-mcpu=3Dcortex-a35']], >>>> - ['0xd05', ['-mcpu=3Dcortex-a55']], >>>> - ['0xd07', ['-mcpu=3Dcortex-a57']], >>>> - ['0xd08', ['-mcpu=3Dcortex-a72']], >>>> - ['0xd09', ['-mcpu=3Dcortex-a73']], >>>> - ['0xd0a', ['-mcpu=3Dcortex-a75']], >>>> - ['0xd0b', ['-mcpu=3Dcortex-a76']], >>>> -] >>>> -machine_args_cavium =3D [ >>>> - ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>>> - ['native', ['-march=3Dnative']], >>>> - ['0xa1', ['-mcpu=3Dthunderxt88']], >>>> - ['0xa2', ['-mcpu=3Dthunderxt81']], >>>> - ['0xa3', ['-mcpu=3Dthunderxt83']]] >>>> - >>>> flags_common_default =3D [ >>>> # Accelarate rte_memcpy. Be sure to run unit test >>> (memcpy_perf_autotest) >>>> # to determine the best threshold in code. Refer to notes in source >>>> file @@ -52,12 +33,10 @@ flags_generic =3D [ >>>> ['RTE_USE_C11_MEM_MODEL', true], >>>> ['RTE_CACHE_LINE_SIZE', 128]] >>>> flags_cavium =3D [ >>>> - ['RTE_MACHINE', '"thunderx"'], >>>> ['RTE_CACHE_LINE_SIZE', 128], >>>> ['RTE_MAX_NUMA_NODES', 2], >>>> ['RTE_MAX_LCORE', 96], >>>> - ['RTE_MAX_VFIO_GROUPS', 128], >>>> - ['RTE_USE_C11_MEM_MODEL', false]] >>>> + ['RTE_MAX_VFIO_GROUPS', 128]] >>>> flags_dpaa =3D [ >>>> ['RTE_MACHINE', '"dpaa"'], >>>> ['RTE_USE_C11_MEM_MODEL', true], >>>> @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ >>>> ['RTE_MAX_NUMA_NODES', 1], >>>> ['RTE_MAX_LCORE', 16], >>>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] >>>> +flags_default_extra =3D [] >>>> +flags_thunderx_extra =3D [ >>>> + ['RTE_MACHINE', '"thunderx"'], >>>> + ['RTE_USE_C11_MEM_MODEL', false]] >>>> + >>>> +machine_args_generic =3D [ >>>> + ['default', ['-march=3Darmv8-a+crc+crypto']], >>>> + ['native', ['-march=3Dnative']], >>>> + ['0xd03', ['-mcpu=3Dcortex-a53']], >>>> + ['0xd04', ['-mcpu=3Dcortex-a35']], >>>> + ['0xd07', ['-mcpu=3Dcortex-a57']], >>>> + ['0xd08', ['-mcpu=3Dcortex-a72']], >>>> + ['0xd09', ['-mcpu=3Dcortex-a73']], >>>> + ['0xd0a', ['-mcpu=3Dcortex-a75']]] >>>> + >>>> +machine_args_cavium =3D [ >>>> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], >>>> + ['native', ['-march=3Dnative']], >>>> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], >>>> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], >>>> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >>>>=20 >>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page >>>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic, >>>> machine_args_generic] @@ -157,8 +157,16 @@ else >>>> endif >>>> foreach marg: machine[2] >>>> if marg[0] =3D=3D impl_pn >>>> - foreach f: marg[1] >>>> - machine_args +=3D f >>>> + foreach flag: marg[1] >>>> + if cc.has_argument(flag) >>>> + machine_args +=3D flag >>>> + endif >>>> + endforeach >>>> + # Apply any extra machine specific flags. >>>> + foreach flag: marg.get(2, flags_default_extra) >>>> + if flag.length() > 0 >>>> + dpdk_conf.set(flag[0], flag[1]) >>>> + endif >>>=20 >>> Let me continue the discussion from v7 here. >>> Seems I wan't clear enough. >>>=20 >>> Let me take an example. If the host is thunderx2 (0xaf) and compiler is= older >>> than v7, flags_thunderx2_extra isn't set. This means, for example, >>> RTE_CACHE_LINE_SIZE will still be 128. Is that what you want? >>> RTE_CACHE_LINE_SIZE has nothing to do with compiler support and you mig= ht >>> want to set it regardless of gcc version. You could skip setting -mcpu = with setting >>> the extra flags. >>>=20 >>=20 >> Thanks for the detailed explanation. >> I think since we have the check to skip mcpu flag when cc doesn't suppor= t it (cc.has_argument(flag)) >> It will be safe to remove=20 >> ` >> # Primary part number based mcpu flags are supported >> # for gcc versions > 7 >> if cc.version().version_compare( >> '<7.0') or cmd_output.length() =3D=3D 0 >> if not meson.is_cross_build() and arm_force_native_march = =3D=3D true >> impl_pn =3D 'native' >> else >> impl_pn =3D 'default' >> endif >> endif >> ` >=20 > +1 I've tested it but still have an issue with old gcc. Even if -mcpu isn't set due to cc.has_argument(), -march isn't set either. So, it spews error due to lack of CRC feature. -march should have '+crc'. The error I got was: > ninja: Entering directory `build' > [942/1452] Compiling C object 'drivers/drivers...c@sta/net_softnic_rte_et= h_softnic_action.c.o'. > FAILED: drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic_rte_eth_soft= nic_action.c.o > cc -Idrivers/drivers@@tmp_rte_pmd_softnic@sta -Idrivers -I../drivers -Idr= ivers/net/softnic -I../drivers/net/softnic -Ilib/librte_ethdev -I../lib/lib= rte_ethdev -I. -I../ -Iconfig -I../config-Ilib/librte_eal/common/include -I= ../lib/librte_eal/common/include -I../lib/librte_eal/linux/eal/include -Ili= b/librte_eal/common -I../lib/librte_eal/common -Ilib/librte_eal/ > common/include/arch/arm -I../lib/librte_eal/common/include/arch/arm -Ilib= /librte_eal -I../lib/librte_eal -Ilib/librte_kvargs -I../lib/librte_kvargs = -Ilib/librte_net -I../lib/librte_net -Ilib/librte_mbuf -I../lib/librte_mbuf= -Ilib/librte_mempool -I../lib/librte_mempool -Ilib/librte_ring -I../lib/li= brte_ring -Ilib/librte_cmdline -I../lib/librte_cmdline -Ilib/lib > rte_meter -I../lib/librte_meter -Idrivers/bus/pci -I../drivers/bus/pci -I= ../drivers/bus/pci/linux -Ilib/librte_pci -I../lib/librte_pci -Idrivers/bus= /vdev -I../drivers/bus/vdev -Ilib/librte_pipeline -I../lib/librte_pipeline = -Ilib/librte_port -I../lib/librte_port -Ilib/librte_sched -I../lib/librte_s= ched -Ilib/librte_ip_frag -I../lib/librte_ip_frag -Ilib/librte_h > ash -I../lib/librte_hash -Ilib/librte_cryptodev -I../lib/librte_cryptodev= -Ilib/librte_kni -I../lib/librte_kni -Ilib/librte_table -I../lib/librte_ta= ble -Ilib/librte_lpm -I../lib/librte_lpm -Ilib/librte_acl -I../lib/librte_a= cl -pipe -D_FILE_OFFSET_BITS=3D64 -Wall -Winvalid-pch -O3 -include rte_conf= ig.h -Wsign-compare -Wcast-qual -fPIC -D_GNU_SOURCE -DALLOW_EXPERI > MENTAL_API -MD -MQ 'drivers/drivers@@tmp_rte_pmd_softnic@sta/net_softnic= _rte_eth_softnic_action.c.o' -MF 'drivers/drivers@@tmp_rte_pmd_softnic@sta/= net_softnic_rte_eth_softnic_action.c.o.d' -o 'drivers/drivers@@tmp_rte_pmd_= softnic@sta/net_softnic_rte_eth_softnic_action.c.o' -c ../drivers/net/softn= ic/rte_eth_softnic_action.c > {standard input}: Assembler messages: > {standard input}:14: Error: selected processor does not support `crc32cx = w3,w3,x0' > {standard input}:37: Error: selected processor does not support `crc32cx = w1,w1,x3' > {standard input}:40: Error: selected processor does not support `crc32cx = w0,w0,x2' My machine has 0x41(Arm) and 0xd08(cortex-a72). gcc is '4.8.5 20150623 (Red= Hat 4.8.5-28)' Thanks, Yongseok >=20 >>=20 >> The command output check can also be removed as it is handled when calli= ng the command script itself. >=20 > +1 >=20 >>=20 >> Thoughts? >>=20 >> PS. I think the safest way to set CACHELINE_SIZE is to read the cache ty= pe register[1] but sadly only few latest kernels=20 >> have the support through sysfs (/sys/devices/system/cpu/cpu0/cache/index= 0/coherency_line_size)=20 >=20 > +1 >=20 > In summary, +3. LoL >=20 > I'll also submit a patch to change the default cacheline size of cortex-a= 72 with the new flags_*_extra[] >=20 >=20 > thanks, > Yongseok