From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id C6AAE1B3BB for ; Tue, 4 Dec 2018 06:44:11 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2018 21:44:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,312,1539673200"; d="scan'208";a="107079183" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 03 Dec 2018 21:44:10 -0800 Received: from bgsmsx106.gar.corp.intel.com (10.223.43.196) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 3 Dec 2018 21:44:10 -0800 Received: from bgsmsx101.gar.corp.intel.com ([169.254.1.234]) by BGSMSX106.gar.corp.intel.com ([169.254.1.112]) with mapi id 14.03.0415.000; Tue, 4 Dec 2018 11:14:07 +0530 From: "Varghese, Vipin" To: "Varghese, Vipin" , "Lu, Wenzhuo" , "dev@dpdk.org" CC: "Lu, Wenzhuo" , "Yang, Qiming" , "Li, Xiaoyun" , "Wu, Jingjing" Thread-Topic: [dpdk-dev] [PATCH v2 16/20] net/ice: support basic RX/TX Thread-Index: AQHUitaaZLQCoCTd90O7JG2f+HtaV6VuEZIggAABXVA= Date: Tue, 4 Dec 2018 05:44:07 +0000 Message-ID: <4C9E0AB70F954A408CC4ADDBF0F8FA7D4D2C45EC@BGSMSX101.gar.corp.intel.com> References: <1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com> <1543820821-108122-1-git-send-email-wenzhuo.lu@intel.com> <1543820821-108122-17-git-send-email-wenzhuo.lu@intel.com> <4C9E0AB70F954A408CC4ADDBF0F8FA7D4D2C45D8@BGSMSX101.gar.corp.intel.com> In-Reply-To: <4C9E0AB70F954A408CC4ADDBF0F8FA7D4D2C45D8@BGSMSX101.gar.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWE1ZTZiMGEtNzI1My00MDNlLTlkNDItZTVjMDgzYjY3YTdmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiS0RyOEFjdnBpQW56SUxyaFZjR3R4NUFKTFdOTFVcL0ptbUpyczhcL0FVQnlRek1tVm1FeUhMYnlGZm1TZ3YzYlhyIn0= dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.223.10.10] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 16/20] net/ice: support basic RX/TX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Dec 2018 05:44:12 -0000 May this logic is just to allocate the initial descriptor and not actual, i= f yes please ignore my comments. > -----Original Message----- > From: dev On Behalf Of Varghese, Vipin > Sent: Tuesday, December 4, 2018 11:12 AM > To: Lu, Wenzhuo ; dev@dpdk.org > Cc: Lu, Wenzhuo ; Yang, Qiming > ; Li, Xiaoyun ; Wu, Jingjing > > Subject: Re: [dpdk-dev] [PATCH v2 16/20] net/ice: support basic RX/TX >=20 > snipped > > +uint16_t > > +ice_recv_pkts(void *rx_queue, > > + struct rte_mbuf **rx_pkts, > > + uint16_t nb_pkts) > > +{ > > + struct ice_rx_queue *rxq =3D rx_queue; > > + volatile union ice_rx_desc *rx_ring =3D rxq->rx_ring; > > + volatile union ice_rx_desc *rxdp; > > + union ice_rx_desc rxd; > > + struct ice_rx_entry *sw_ring =3D rxq->sw_ring; > > + struct ice_rx_entry *rxe; > > + struct rte_mbuf *nmb; /* new allocated mbuf */ > > + struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */ > > + uint16_t rx_id =3D rxq->rx_tail; > > + uint16_t nb_rx =3D 0; > > + uint16_t nb_hold =3D 0; > > + uint16_t rx_packet_len; > > + uint32_t rx_status; > > + uint64_t qword1; > > + uint64_t dma_addr; > > + uint64_t pkt_flags =3D 0; > > + uint32_t *ptype_tbl =3D rxq->vsi->adapter->ptype_tbl; > > + struct rte_eth_dev *dev; > > + > > + while (nb_rx < nb_pkts) { > > + rxdp =3D &rx_ring[rx_id]; > > + qword1 =3D rte_le_to_cpu_64(rxdp- > > >wb.qword1.status_error_len); > > + rx_status =3D (qword1 & ICE_RXD_QW1_STATUS_M) >> > > + ICE_RXD_QW1_STATUS_S; > > + > > + /* Check the DD bit first */ > > + if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S))) > > + break; > > + > > + /* allocate mbuf */ > > + nmb =3D rte_mbuf_raw_alloc(rxq->mp); > > + if (unlikely(!nmb)) { > > + dev =3D ICE_VSI_TO_ETH_DEV(rxq->vsi); > > + dev->data->rx_mbuf_alloc_failed++; > > + break; > > + } >=20 > Should we check if the received packet length is greater than mbug pkt_le= n then > we need bulk alloc with n_segs? >=20 > > + rxd =3D *rxdp; /* copy descriptor in ring to temp variable*/ > > + > > + nb_hold++; > > + rxe =3D &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */ > > + rx_id++; > > + if (unlikely(rx_id =3D=3D rxq->nb_rx_desc)) > > + rx_id =3D 0; > > + rxm =3D rxe->mbuf; > > + rxe->mbuf =3D nmb; > > + dma_addr =3D > > + rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb)); > > + > > + /** > > + * fill the read format of descriptor with physic address in > > + * new allocated mbuf: nmb > > + */ > > + rxdp->read.hdr_addr =3D 0; > > + rxdp->read.pkt_addr =3D dma_addr; > > + > > + /* calculate rx_packet_len of the received pkt */ > > + rx_packet_len =3D ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >> > > + ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len; > > + > > + /* fill old mbuf with received descriptor: rxd */ > > + rxm->data_off =3D RTE_PKTMBUF_HEADROOM; > > + rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, > > RTE_PKTMBUF_HEADROOM)); > > + rxm->nb_segs =3D 1; >=20 > Same comment for above for multi segment alloc for larger packets or smal= ler > pkt_len in mempool? >=20 > Snipped