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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 29-Jul-24 12:47 PM, Aakash Sasidharan wrote: > In case of event mode operations where event device can help in atomic > sequence number increment across cores, sequence number need to be > provided by the application instead of being updated in rte_ipsec or the > PMD. > > To support this, two new APIs rte_ipsec_pkt_crypto_sqn_assign and > rte_ipsec_pkt_crypto_xprepare are introduced decoupling the seq no update > functionality from the existing rte_ipsec_pkt_crypto_prepare API. > Additionally, a new flag ``RTE_IPSEC_SAFLAG_SQN_ASSIGN_DISABLE`` will be > added to allow disabling of internal sequence number update inside IPsec > library. > > Signed-off-by: Aakash Sasidharan > --- Acked-by: Radu Nicolau --------------zPPgku1TAEDeUbwNDrQqGW1O Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: 7bit


On 29-Jul-24 12:47 PM, Aakash Sasidharan wrote:
In case of event mode operations where event device can help in atomic
sequence number increment across cores, sequence number need to be
provided by the application instead of being updated in rte_ipsec or the
PMD.

To support this, two new APIs rte_ipsec_pkt_crypto_sqn_assign and
rte_ipsec_pkt_crypto_xprepare are introduced decoupling the seq no update
functionality from the existing rte_ipsec_pkt_crypto_prepare API.
Additionally, a new flag ``RTE_IPSEC_SAFLAG_SQN_ASSIGN_DISABLE`` will be
added to allow disabling of internal sequence number update inside IPsec
library.

Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
---
Acked-by: Radu Nicolau <radu.nicolau@intel.com> --------------zPPgku1TAEDeUbwNDrQqGW1O--