From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <olivier.matz@6wind.com>
Received: from mail.droids-corp.org (zoll.droids-corp.org [94.23.50.67])
 by dpdk.org (Postfix) with ESMTP id 3BDAA58DD
 for <dev@dpdk.org>; Thu, 27 Mar 2014 17:45:33 +0100 (CET)
Received: from was59-1-82-226-113-214.fbx.proxad.net ([82.226.113.214]
 helo=[192.168.0.10]) by mail.droids-corp.org with esmtpsa
 (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80)
 (envelope-from <olivier.matz@6wind.com>) id 1WTDTb-0005nz-GG
 for dev@dpdk.org; Thu, 27 Mar 2014 17:48:27 +0100
Message-ID: <53345655.9030907@6wind.com>
Date: Thu, 27 Mar 2014 17:48:21 +0100
From: Olivier MATZ <olivier.matz@6wind.com>
User-Agent: Mozilla/5.0 (X11; Linux x86_64;
 rv:17.0) Gecko/20131103 Icedove/17.0.10
MIME-Version: 1.0
To: "dev@dpdk.org" <dev@dpdk.org>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Content-Transfer-Encoding: 7bit
Subject: [dpdk-dev] memory barriers in rte_ring
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: patches and discussions about DPDK <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
X-List-Received-Date: Thu, 27 Mar 2014 16:45:33 -0000

Hi,

The commit 286bd05bf7 [1] removed the memory barriers in the ring
functions. This patch is present in DPDK since version 1.4.0r0, so I
guess it does not cause any issue.

But after checking the excellent Linux kernel documentation about memory
barriers [2], I'm wondering why memory barriers would not be required in
that case.

To illustrate the previous behavior (before dpdk 1.4):

   ring_enqueue()
     - move producer_head to reserve space in ring (atomically if
       multi producers)
     - write objects between producer_head and producer_tail
     - wmb() to ensure that STORE operations are issued
     - write producer_tail

   ring_dequeue()
     - move consumer_head (atomically if multi consumers)
     - rmb() to ensure that LOAD operations are issued: the read of
       consumer_head must occur before the reading of objects ptrs.
       In fact, rmb() is probably not needed here because knowing the
       value of consumer_head is required before reading the objects
       table.
     - read objects between consumer_head and consumer_tail
     - write consumer_tail

The memory barriers have been removed, but in my understanding at least
the wmb() would be needed according to the generic memory barrier
documentation. Maybe this is not needed on newest Intel processors?
Could anyone from Intel enlight me on this?

Thanks & regards,
Olivier


[1] 
http://dpdk.org/browse/dpdk/commit/lib/librte_ring/rte_ring.h?id=286bd05bf70d1da1b6017007276c267a1e012c1d

[2] http://lxr.free-electrons.com/source/Documentation/memory-barriers.txt