From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.droids-corp.org (zoll.droids-corp.org [94.23.50.67]) by dpdk.org (Postfix) with ESMTP id 6E97F58DD for ; Thu, 27 Mar 2014 20:44:49 +0100 (CET) Received: from was59-1-82-226-113-214.fbx.proxad.net ([82.226.113.214] helo=[192.168.0.10]) by mail.droids-corp.org with esmtpsa (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1WTGH5-0005ty-L2; Thu, 27 Mar 2014 20:47:43 +0100 Message-ID: <53348059.6000505@6wind.com> Date: Thu, 27 Mar 2014 20:47:37 +0100 From: Olivier MATZ User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20131103 Icedove/17.0.10 MIME-Version: 1.0 To: Stephen Hemminger References: <53345655.9030907@6wind.com> <20140327120620.07f1496b@samsung-9> In-Reply-To: <20140327120620.07f1496b@samsung-9> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] memory barriers in rte_ring X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Mar 2014 19:44:49 -0000 Hi Stephen, On 03/27/2014 08:06 PM, Stephen Hemminger wrote: > Long answer: for the multple CPU access ring, it is equivalent to smp_wmb and smp_rmb > in Linux kernel. For x86 where DPDK is used, this can normally be replaced by simpler > compiler barrier. In kernel there is a special flage X86_OOSTORE which is only enabled > for a few special cases, for most cases it is not. When cpu doesnt do out of order > stores, there are no cases where other cpu will see wrong state. Thank you for this clarification. So, if I understand properly, all usages of rte_*mb() sequencing memory operations between CPUs could be replaced by a compiler barrier. On the other hand, if the memory is also accessed by a device, a memory barrier has to be used. Olivier