From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D53DA046B for ; Tue, 20 Aug 2019 17:07:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7FF401BEFC; Tue, 20 Aug 2019 17:07:41 +0200 (CEST) Received: from mta123.f1.k8.com.br (mta123.f1.k8.com.br [187.73.32.199]) by dpdk.org (Postfix) with ESMTP id 718183423 for ; Fri, 16 Aug 2019 20:50:59 +0200 (CEST) Received: from [192.168.86.43] (pool-108-20-205-122.bstnma.fios.verizon.net [108.20.205.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtpz.f1.k8.com.br (Postfix) with ESMTPSA id 009EC6007C; Fri, 16 Aug 2019 18:50:49 +0000 (UTC) X-DKIM: OpenDKIM Filter v2.6.8 smtpz.f1.k8.com.br 009EC6007C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digirati.com.br; s=default; t=1565981457; bh=b9xagwneFcpSxYFTMK9h4zqFtuFeJEyp5IdHt1wsVd4=; h=Subject:To:From:Date:Feedback-ID; b=TWVU6M22S5ToSajg9jCzVopw4cJsTN69p0y4YCh4JvIGqZVvnwfgRIFjoplEWal73 Q4LkIjvbCVkG/IHYyspiQKdxkclp73gnMAnzIcA15mBe9oQt5hwn15VxNtmQxz6ODq +PGrQTGacVdac90/mPmVmLDd84oNixlZ1cK7hgCE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=k8.com.br; s=default; t=1565981457; bh=b9xagwneFcpSxYFTMK9h4zqFtuFeJEyp5IdHt1wsVd4=; h=Subject:To:From:Date:Feedback-ID; b=iTK72P8N7RoDHH8Bpb17NGgjTY+2EiaXg8SWsXkk5yWBka1K9KOLpNf7vqZU+ZfgJ MXdtb4PRGBXIq9xIgrxle/SezKbSzpFk6EWoPU4HID6m2MYjSOiKxH9hEB5wpIhIFb oRHfnL5kDrBC0mUlVbVcyNfmSUV40Y3s992gt6qg= To: Konstantin Ananyev , dev@dpdk.org Cc: olivier.matz@6wind.com, anatoly.burakov@intel.com, vipin.varghese@intel.com References: <20190816125304.29719-1-konstantin.ananyev@intel.com> <20190816125304.29719-2-konstantin.ananyev@intel.com> From: Michel Machado Organization: Digirati Internet LTDA. Message-ID: <553c64ff-f99d-8fa1-8e0b-450c1793177f@digirati.com.br> Date: Fri, 16 Aug 2019 14:50:47 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190816125304.29719-2-konstantin.ananyev@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: pt-BR Content-Transfer-Encoding: 7bit X-HN-S: bWljaGVsQGRpZ2lyYXRpLmNvbS5icg== X-HN-R: ZGV2QGRwZGsub3Jn a29uc3RhbnRpbi5hbmFueWV2QGludGVsLmNvbQ== Feedback-ID: MjAxOTA4MTY=:bWljaGVsQGRpZ2lyYXRpLmNvbS5icg==:ZGlnaXJhdGkuY29tLmJy:k8networks X-Mailman-Approved-At: Tue, 20 Aug 2019 17:07:37 +0200 Subject: Re: [dpdk-dev] [PATCH 1/3] eal: move CACHE and IOVA related definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Acked-by: Michel Machado [ ]'s Michel Machado On 8/16/19 8:53 AM, Konstantin Ananyev wrote: > Right now RTE_CACHE_ and IOVA definitions are located inside rte_memory.h > That might cause an unwanted inclusions of arch/os specific header files. > See [1] for particular problem example. > Probably the simplest way to deal with such problems - > move these definitions into rte_commmon.h > > Note that this move doesn't introduce any change in functionality. > > [1] https://bugs.dpdk.org/show_bug.cgi?id=321 > > Suggested-by: Vipin Varghese > Signed-off-by: Konstantin Ananyev > --- > lib/librte_eal/common/include/rte_common.h | 44 ++++++++++++++++++++++ > lib/librte_eal/common/include/rte_memory.h | 38 ------------------- > 2 files changed, 44 insertions(+), 38 deletions(-) > > diff --git a/lib/librte_eal/common/include/rte_common.h b/lib/librte_eal/common/include/rte_common.h > index 05a3a6401..c275093d7 100644 > --- a/lib/librte_eal/common/include/rte_common.h > +++ b/lib/librte_eal/common/include/rte_common.h > @@ -291,6 +291,50 @@ rte_is_aligned(void *ptr, unsigned align) > */ > #define RTE_BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) > > +/*********** RTE_CACHE related macros ********/ > + > +#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */ > + > +#define RTE_CACHE_LINE_ROUNDUP(size) \ > + (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / \ > + RTE_CACHE_LINE_SIZE)) > +/**< Return the first cache-aligned value greater or equal to size. */ > + > +/**< Cache line size in terms of log2 */ > +#if RTE_CACHE_LINE_SIZE == 64 > +#define RTE_CACHE_LINE_SIZE_LOG2 6 > +#elif RTE_CACHE_LINE_SIZE == 128 > +#define RTE_CACHE_LINE_SIZE_LOG2 7 > +#else > +#error "Unsupported cache line size" > +#endif > + > +#define RTE_CACHE_LINE_MIN_SIZE 64 /**< Minimum Cache line size. */ > + > +/** > + * Force alignment to cache line. > + */ > +#define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) > + > +/** > + * Force minimum cache line alignment. > + */ > +#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) > + > +/*********** PA/IOVA type definitions ********/ > + > +typedef uint64_t phys_addr_t; /**< Physical address. */ > +#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) > +/** > + * IO virtual address type. > + * When the physical addressing mode (IOVA as PA) is in use, > + * the translation from an IO virtual address (IOVA) to a physical address > + * is a direct mapping, i.e. the same value. > + * Otherwise, in virtual mode (IOVA as VA), an IOMMU may do the translation. > + */ > +typedef uint64_t rte_iova_t; > +#define RTE_BAD_IOVA ((rte_iova_t)-1) > + > /** > * Combines 32b inputs most significant set bits into the least > * significant bits to construct a value with the same MSBs as x > diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h > index 4717dcb43..38e00e382 100644 > --- a/lib/librte_eal/common/include/rte_memory.h > +++ b/lib/librte_eal/common/include/rte_memory.h > @@ -39,44 +39,6 @@ enum rte_page_sizes { > }; > > #define SOCKET_ID_ANY -1 /**< Any NUMA socket. */ > -#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */ > - > -#define RTE_CACHE_LINE_ROUNDUP(size) \ > - (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) > -/**< Return the first cache-aligned value greater or equal to size. */ > - > -/**< Cache line size in terms of log2 */ > -#if RTE_CACHE_LINE_SIZE == 64 > -#define RTE_CACHE_LINE_SIZE_LOG2 6 > -#elif RTE_CACHE_LINE_SIZE == 128 > -#define RTE_CACHE_LINE_SIZE_LOG2 7 > -#else > -#error "Unsupported cache line size" > -#endif > - > -#define RTE_CACHE_LINE_MIN_SIZE 64 /**< Minimum Cache line size. */ > - > -/** > - * Force alignment to cache line. > - */ > -#define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE) > - > -/** > - * Force minimum cache line alignment. > - */ > -#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE) > - > -typedef uint64_t phys_addr_t; /**< Physical address. */ > -#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) > -/** > - * IO virtual address type. > - * When the physical addressing mode (IOVA as PA) is in use, > - * the translation from an IO virtual address (IOVA) to a physical address > - * is a direct mapping, i.e. the same value. > - * Otherwise, in virtual mode (IOVA as VA), an IOMMU may do the translation. > - */ > -typedef uint64_t rte_iova_t; > -#define RTE_BAD_IOVA ((rte_iova_t)-1) > > /** > * Physical memory segment descriptor. >