From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD82A4404F; Wed, 12 Jun 2024 17:05:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2701640E41; Wed, 12 Jun 2024 17:03:38 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 8FA5240EE3 for ; Wed, 12 Jun 2024 17:03:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204616; x=1749740616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iOdlMIM6uqfRRfDrjxRw7LbzDWijDxzBDl1jQN/oSPk=; b=J8At+LRo7yKkt9Y91cTRV0l06wlKTwHSGh2OJcOJsi5JVW4M10fSVxqB khexG/zVFcT+h0ijna9NcQM3Ce8hLva6S4yd6WzemGkC9V91P0uNP56if 37DV6jAgRIBC9Hyw7yBrQwlmjZdYmomqcVYkqmWDz7+Ih7tAiFg+FcbAB NtGb8ajbktKXZ1ro2iRzqd858qGB2o7xepQ7zwrSfQ/+5/qTD2jA2+5HV Mb5NSRT6vW8aFmrxaHj6vyClhdlqyHGYCBC5xfFP38uaHyHvc6gwXop6C E4UXFQEx42IixqoaByIWwDAYcpPypdiXYoZ2ypWwtYzEQBOaIjBBnA6kO Q==; X-CSE-ConnectionGUID: sNrZJzfRQaGdemDOunf9rw== X-CSE-MsgGUID: XdXGxVwbS4iRccII6U+7Mw== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32459142" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32459142" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:03:35 -0700 X-CSE-ConnectionGUID: VELzLqbrTAKSti3jjpcLTA== X-CSE-MsgGUID: 7KeAR0rFQbGYXKpGeNI50w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39924884" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:03:32 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Paul Greenwalt Subject: [PATCH v2 011/148] net/ice/base: fix get media type Date: Wed, 12 Jun 2024 16:00:05 +0100 Message-ID: <55b6751736d5f47676da021427bec3d2039bf90e.1718204528.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes The use of get link status PHY type for determining the media type can result in incorrect reporting the incorrect media type. This can happen for a couple reasons: 1. The get link states current PHY type field can return non-PHY type values (i.e. bit 127 indicates link state disabled, and bit 126 indicates PHY is in auto-negotiation state) 2. Forced link configurations can result in incorrectly mapping on media type (i.e. forcing optical link modes on copper media) Add the media type ICE_MEDIA_NONE. As part of this patch add the new PHY type bits needed for 200G architecture. Signed-off-by: Paul Greenwalt Signed-off-by: Alice Michael Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_adminq_cmd.h | 13 +- drivers/net/ice/base/ice_common.c | 244 ++++++++++---------------- drivers/net/ice/base/ice_type.h | 94 +++++++++- 3 files changed, 195 insertions(+), 156 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 844e90bbce..56c9a4813e 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1398,7 +1398,18 @@ struct ice_aqc_get_phy_caps { #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) -#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 +#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) +#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) +#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) +#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) +#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) +#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) +#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) +#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) +#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13) +#define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14) +#define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15) +#define ICE_PHY_TYPE_HIGH_MAX_INDEX 15 struct ice_aqc_get_phy_caps_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 113620ff0a..1fe9bebe7d 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -345,6 +345,93 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, return 0; } +/** + * ice_phy_maps_to_media + * @phy_type_low: PHY type low bits + * @phy_type_high: PHY type high bits + * @media_mask_low: media type PHY type low bitmask + * @media_mask_high: media type PHY type high bitmask + * + * Return true if PHY type [low|high] bits are only of media type PHY types + * [low|high] bitmask. + */ +static bool +ice_phy_maps_to_media(u64 phy_type_low, u64 phy_type_high, + u64 media_mask_low, u64 media_mask_high) +{ + /* check if a PHY type exist for media type */ + if (!(phy_type_low & media_mask_low || + phy_type_high & media_mask_high)) + return false; + + /* check that PHY types are only of media type */ + if (!(phy_type_low & ~media_mask_low) && + !(phy_type_high & ~media_mask_high)) + return true; + + return false; +} + +/** + * ice_set_media_type - Sets media type + * @pi: port information structure + * + * Set ice_port_info PHY media type based on PHY type. This should be called + * from Get PHY caps with media. + */ +static void ice_set_media_type(struct ice_port_info *pi) +{ + enum ice_media_type *media_type; + u64 phy_type_high, phy_type_low; + + phy_type_high = pi->phy.phy_type_high; + phy_type_low = pi->phy.phy_type_low; + media_type = &pi->phy.media_type; + + /* if no media, then media type is NONE */ + if (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE)) + *media_type = ICE_MEDIA_NONE; + /* else if PHY types are only BASE-T, then media type is BASET */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_BASET_PHY_TYPE_LOW_M, 0)) + *media_type = ICE_MEDIA_BASET; + /* else if any PHY type is BACKPLANE, then media type is BACKPLANE */ + else if (phy_type_low & ICE_MEDIA_BP_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_BP_PHY_TYPE_HIGH_M) + *media_type = ICE_MEDIA_BACKPLANE; + /* else if PHY types are only optical, or optical and C2M, then media + * type is FIBER + */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_OPT_PHY_TYPE_LOW_M, + ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) || + ((phy_type_low & ICE_MEDIA_OPT_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) && + (phy_type_low & ICE_MEDIA_C2M_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M))) + *media_type = ICE_MEDIA_FIBER; + /* else if PHY types are only DA, or DA and C2C, then media type DA */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_DAC_PHY_TYPE_LOW_M, + ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) || + ((phy_type_low & ICE_MEDIA_DAC_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) && + (phy_type_low & ICE_MEDIA_C2C_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M))) + *media_type = ICE_MEDIA_DA; + /* else if PHY types are only C2M or only C2C, then media is AUI */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_C2M_PHY_TYPE_LOW_M, + ICE_MEDIA_C2M_PHY_TYPE_HIGH_M) || + ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_C2C_PHY_TYPE_LOW_M, + ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)) + *media_type = ICE_MEDIA_AUI; + + else + *media_type = ICE_MEDIA_UNKNOWN; +} + /** * ice_aq_get_phy_caps - returns PHY capabilities * @pi: port information structure @@ -429,6 +516,9 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, sizeof(pi->phy.link_info.module_type), ICE_NONDMA_TO_NONDMA); + ice_set_media_type(pi); + ice_debug(hw, ICE_DBG_LINK, "%s: media_type = 0x%x\n", prefix, + pi->phy.media_type); } return status; @@ -534,156 +624,6 @@ ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, return ICE_ERR_DOES_NOT_EXIST; } -/** - * ice_is_media_cage_present - * @pi: port information structure - * - * Returns true if media cage is present, else false. If no cage, then - * media type is backplane or BASE-T. - */ -static bool ice_is_media_cage_present(struct ice_port_info *pi) -{ - struct ice_aqc_get_link_topo *cmd; - struct ice_aq_desc desc; - - cmd = &desc.params.get_link_topo; - - ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); - - cmd->addr.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << - ICE_AQC_LINK_TOPO_NODE_CTX_S); - - /* set node type */ - cmd->addr.topo_params.node_type_ctx |= - (ICE_AQC_LINK_TOPO_NODE_TYPE_M & - ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE); - - /* Node type cage can be used to determine if cage is present. If AQC - * returns error (ENOENT), then no cage present. If no cage present then - * connection type is backplane or BASE-T. - */ - return ice_aq_get_netlist_node(pi->hw, cmd, NULL, NULL); -} - -/** - * ice_get_media_type - Gets media type - * @pi: port information structure - */ -static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) -{ - struct ice_link_status *hw_link_info; - - if (!pi) - return ICE_MEDIA_UNKNOWN; - - hw_link_info = &pi->phy.link_info; - if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) - /* If more than one media type is selected, report unknown */ - return ICE_MEDIA_UNKNOWN; - - if (hw_link_info->phy_type_low) { - /* 1G SGMII is a special case where some DA cable PHYs - * may show this as an option when it really shouldn't - * be since SGMII is meant to be between a MAC and a PHY - * in a backplane. Try to detect this case and handle it - */ - if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && - (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == - ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || - hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == - ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) - return ICE_MEDIA_DA; - - switch (hw_link_info->phy_type_low) { - case ICE_PHY_TYPE_LOW_1000BASE_SX: - case ICE_PHY_TYPE_LOW_1000BASE_LX: - case ICE_PHY_TYPE_LOW_10GBASE_SR: - case ICE_PHY_TYPE_LOW_10GBASE_LR: - case ICE_PHY_TYPE_LOW_25GBASE_SR: - case ICE_PHY_TYPE_LOW_25GBASE_LR: - case ICE_PHY_TYPE_LOW_40GBASE_SR4: - case ICE_PHY_TYPE_LOW_40GBASE_LR4: - case ICE_PHY_TYPE_LOW_50GBASE_SR2: - case ICE_PHY_TYPE_LOW_50GBASE_LR2: - case ICE_PHY_TYPE_LOW_50GBASE_SR: - case ICE_PHY_TYPE_LOW_50GBASE_FR: - case ICE_PHY_TYPE_LOW_50GBASE_LR: - case ICE_PHY_TYPE_LOW_100GBASE_SR4: - case ICE_PHY_TYPE_LOW_100GBASE_LR4: - case ICE_PHY_TYPE_LOW_100GBASE_SR2: - case ICE_PHY_TYPE_LOW_100GBASE_DR: - return ICE_MEDIA_FIBER; - case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: - case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: - case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: - case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: - case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: - case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: - case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: - case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: - return ICE_MEDIA_FIBER; - case ICE_PHY_TYPE_LOW_100BASE_TX: - case ICE_PHY_TYPE_LOW_1000BASE_T: - case ICE_PHY_TYPE_LOW_2500BASE_T: - case ICE_PHY_TYPE_LOW_5GBASE_T: - case ICE_PHY_TYPE_LOW_10GBASE_T: - case ICE_PHY_TYPE_LOW_25GBASE_T: - return ICE_MEDIA_BASET; - case ICE_PHY_TYPE_LOW_10G_SFI_DA: - case ICE_PHY_TYPE_LOW_25GBASE_CR: - case ICE_PHY_TYPE_LOW_25GBASE_CR_S: - case ICE_PHY_TYPE_LOW_25GBASE_CR1: - case ICE_PHY_TYPE_LOW_40GBASE_CR4: - case ICE_PHY_TYPE_LOW_50GBASE_CR2: - case ICE_PHY_TYPE_LOW_50GBASE_CP: - case ICE_PHY_TYPE_LOW_100GBASE_CR4: - case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: - case ICE_PHY_TYPE_LOW_100GBASE_CP2: - return ICE_MEDIA_DA; - case ICE_PHY_TYPE_LOW_25G_AUI_C2C: - case ICE_PHY_TYPE_LOW_40G_XLAUI: - case ICE_PHY_TYPE_LOW_50G_LAUI2: - case ICE_PHY_TYPE_LOW_50G_AUI2: - case ICE_PHY_TYPE_LOW_50G_AUI1: - case ICE_PHY_TYPE_LOW_100G_AUI4: - case ICE_PHY_TYPE_LOW_100G_CAUI4: - if (ice_is_media_cage_present(pi)) - return ICE_MEDIA_AUI; - /* fall-through */ - case ICE_PHY_TYPE_LOW_1000BASE_KX: - case ICE_PHY_TYPE_LOW_2500BASE_KX: - case ICE_PHY_TYPE_LOW_2500BASE_X: - case ICE_PHY_TYPE_LOW_5GBASE_KR: - case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: - case ICE_PHY_TYPE_LOW_10G_SFI_C2C: - case ICE_PHY_TYPE_LOW_25GBASE_KR: - case ICE_PHY_TYPE_LOW_25GBASE_KR1: - case ICE_PHY_TYPE_LOW_25GBASE_KR_S: - case ICE_PHY_TYPE_LOW_40GBASE_KR4: - case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: - case ICE_PHY_TYPE_LOW_50GBASE_KR2: - case ICE_PHY_TYPE_LOW_100GBASE_KR4: - case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: - return ICE_MEDIA_BACKPLANE; - } - } else { - switch (hw_link_info->phy_type_high) { - case ICE_PHY_TYPE_HIGH_100G_AUI2: - case ICE_PHY_TYPE_HIGH_100G_CAUI2: - if (ice_is_media_cage_present(pi)) - return ICE_MEDIA_AUI; - /* fall-through */ - case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: - return ICE_MEDIA_BACKPLANE; - case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: - case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: - return ICE_MEDIA_FIBER; - } - } - return ICE_MEDIA_UNKNOWN; -} - /** * ice_aq_get_link_info * @pi: port information structure @@ -700,7 +640,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, struct ice_aqc_get_link_status_data link_data = { 0 }; struct ice_aqc_get_link_status *resp; struct ice_link_status *li_old, *li; - enum ice_media_type *hw_media_type; struct ice_fc_info *hw_fc_info; bool tx_pause, rx_pause; struct ice_aq_desc desc; @@ -712,7 +651,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, return ICE_ERR_PARAM; hw = pi->hw; li_old = &pi->phy.link_info_old; - hw_media_type = &pi->phy.media_type; li = &pi->phy.link_info; hw_fc_info = &pi->fc; @@ -734,7 +672,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, li->link_speed = LE16_TO_CPU(link_data.link_speed); li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); - *hw_media_type = ice_get_media_type(pi); li->link_info = link_data.link_info; li->link_cfg_err = link_data.link_cfg_err; li->an_info = link_data.an_info; @@ -765,7 +702,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, (unsigned long long)li->phy_type_low); ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", (unsigned long long)li->phy_type_high); - ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index e7bd2215ce..c7ca62bea0 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -211,7 +211,8 @@ enum ice_mac_type { /* Media Types */ enum ice_media_type { - ICE_MEDIA_UNKNOWN = 0, + ICE_MEDIA_NONE = 0, + ICE_MEDIA_UNKNOWN, ICE_MEDIA_FIBER, ICE_MEDIA_BASET, ICE_MEDIA_BACKPLANE, @@ -219,6 +220,97 @@ enum ice_media_type { ICE_MEDIA_AUI, }; +#define ICE_MEDIA_BASET_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100BASE_TX | \ + ICE_PHY_TYPE_LOW_1000BASE_T | \ + ICE_PHY_TYPE_LOW_2500BASE_T | \ + ICE_PHY_TYPE_LOW_5GBASE_T | \ + ICE_PHY_TYPE_LOW_10GBASE_T | \ + ICE_PHY_TYPE_LOW_25GBASE_T) + +#define ICE_MEDIA_C2M_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC | \ + ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC | \ + ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC | \ + ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC | \ + ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC | \ + ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC | \ + ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC | \ + ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) + +#define ICE_MEDIA_C2M_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC | \ + ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \ + ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \ + ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC) + +#define ICE_MEDIA_OPT_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_SX | \ + ICE_PHY_TYPE_LOW_1000BASE_LX | \ + ICE_PHY_TYPE_LOW_10GBASE_SR | \ + ICE_PHY_TYPE_LOW_10GBASE_LR | \ + ICE_PHY_TYPE_LOW_25GBASE_SR | \ + ICE_PHY_TYPE_LOW_25GBASE_LR | \ + ICE_PHY_TYPE_LOW_40GBASE_SR4 | \ + ICE_PHY_TYPE_LOW_40GBASE_LR4 | \ + ICE_PHY_TYPE_LOW_50GBASE_SR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_LR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_SR | \ + ICE_PHY_TYPE_LOW_50GBASE_LR | \ + ICE_PHY_TYPE_LOW_100GBASE_SR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_LR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_SR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_FR | \ + ICE_PHY_TYPE_LOW_100GBASE_DR) + +#define ICE_MEDIA_OPT_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_200G_SR4 | \ + ICE_PHY_TYPE_HIGH_200G_LR4 | \ + ICE_PHY_TYPE_HIGH_200G_FR4 | \ + ICE_PHY_TYPE_HIGH_200G_DR4 | \ + ICE_PHY_TYPE_HIGH_400GBASE_FR8) + +#define ICE_MEDIA_BP_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_KX | \ + ICE_PHY_TYPE_LOW_2500BASE_KX | \ + ICE_PHY_TYPE_LOW_5GBASE_KR | \ + ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 | \ + ICE_PHY_TYPE_LOW_25GBASE_KR | \ + ICE_PHY_TYPE_LOW_25GBASE_KR_S | \ + ICE_PHY_TYPE_LOW_25GBASE_KR1 | \ + ICE_PHY_TYPE_LOW_40GBASE_KR4 | \ + ICE_PHY_TYPE_LOW_50GBASE_KR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 | \ + ICE_PHY_TYPE_LOW_100GBASE_KR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) + +#define ICE_MEDIA_BP_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 | \ + ICE_PHY_TYPE_HIGH_200G_KR4_PAM4) + +#define ICE_MEDIA_DAC_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_DA | \ + ICE_PHY_TYPE_LOW_25GBASE_CR | \ + ICE_PHY_TYPE_LOW_25GBASE_CR_S | \ + ICE_PHY_TYPE_LOW_25GBASE_CR1 | \ + ICE_PHY_TYPE_LOW_40GBASE_CR4 | \ + ICE_PHY_TYPE_LOW_50GBASE_CR2 | \ + ICE_PHY_TYPE_LOW_100GBASE_CR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 | \ + ICE_PHY_TYPE_LOW_50GBASE_CP | \ + ICE_PHY_TYPE_LOW_100GBASE_CP2) + +#define ICE_MEDIA_DAC_PHY_TYPE_HIGH_M ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 + +#define ICE_MEDIA_C2C_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100M_SGMII | \ + ICE_PHY_TYPE_LOW_1G_SGMII | \ + ICE_PHY_TYPE_LOW_2500BASE_X | \ + ICE_PHY_TYPE_LOW_10G_SFI_C2C | \ + ICE_PHY_TYPE_LOW_25G_AUI_C2C | \ + ICE_PHY_TYPE_LOW_40G_XLAUI | \ + ICE_PHY_TYPE_LOW_50G_LAUI2 | \ + ICE_PHY_TYPE_LOW_50G_AUI2 | \ + ICE_PHY_TYPE_LOW_50G_AUI1 | \ + ICE_PHY_TYPE_LOW_100G_CAUI4 | \ + ICE_PHY_TYPE_LOW_100G_AUI4) + +#define ICE_MEDIA_C2C_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2 | \ + ICE_PHY_TYPE_HIGH_100G_AUI2 | \ + ICE_PHY_TYPE_HIGH_200G_AUI4 | \ + ICE_PHY_TYPE_HIGH_200G_AUI8) + /* Software VSI types. */ enum ice_vsi_type { ICE_VSI_PF = 0, -- 2.43.0