From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 32366C3B0 for ; Wed, 21 Oct 2015 17:47:23 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP; 21 Oct 2015 08:47:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,712,1437462000"; d="scan'208";a="585405590" Received: from bricha3-mobl3.ger.corp.intel.com (HELO [10.237.208.65]) ([10.237.208.65]) by FMSMGA003.fm.intel.com with ESMTP; 21 Oct 2015 08:47:21 -0700 To: Nikita Kalyazin References: <1445350066-31818-1-git-send-email-n.kalyazin@samsung.com> <20151020142951.GA18496@bricha3-MOBL3> <20151021154204.GB27896@kalyazin.rnd.samsung.ru> From: Bruce Richardson Message-ID: <5627B387.4020605@intel.com> Date: Wed, 21 Oct 2015 16:47:19 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151021154204.GB27896@kalyazin.rnd.samsung.ru> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH] vhost: call write barrier before used index update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Oct 2015 15:47:23 -0000 On 21/10/2015 16:42, Nikita Kalyazin wrote: > Hi, > >> This has been discussed a number of times before on list, and the consensus >> seems to be that the correct way to fix this is to introduce a set of specific >> barrier operations that insert the correct barrier type on each architecture, >> i.e. compiler barriers on IA, and full wmbs on architectures that require that. > Linux kernel contains two sets of macros: *mb() and smp_*mb(). As far as > I understand, the former are meant to order memory accesses when interacting > with peripherals (physical NICs in our case), and the latter - to provide > synchronization between CPU cores (applicable for virtual NICs in our case). > smp_*mb() for Intel architecture would be a simple compiler barrier, whereas > for processors with weaker memory model they may use real barrier > instructions. > Maybe implementing barriers similar way would work in DPDK as well? > It should work indeed. Not sure if we need two separate sets of barrier functions, the smb_*mb() might work on their own (certainly for IA, they should do - not sure for other architectures), but I think the general consensus, based on previous discussions, is that this is the direction we want to go in for these barrier issues. /Bruce