From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 67F628E8B for ; Mon, 2 Nov 2015 11:48:03 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 02 Nov 2015 02:47:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,234,1444719600"; d="scan'208";a="592442214" Received: from dhunt5x-mobl3.ger.corp.intel.com (HELO [10.237.208.62]) ([10.237.208.62]) by FMSMGA003.fm.intel.com with ESMTP; 02 Nov 2015 02:47:54 -0800 To: Jerin Jacob References: <1446212826-19425-7-git-send-email-david.hunt@intel.com> <5633798B.2050708@intel.com> <20151030161106.4657232.16920.465@rehivetech.com> <56339AA9.1060505@intel.com> <20151102063209.GC17659@localhost.localdomain> From: "Hunt, David" Message-ID: <56373F59.6080602@intel.com> Date: Mon, 2 Nov 2015 10:47:53 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151102063209.GC17659@localhost.localdomain> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v3 6/6] test: add checks for cpu flags on armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Nov 2015 10:48:04 -0000 On 02/11/2015 06:32, Jerin Jacob wrote: > On Fri, Oct 30, 2015 at 04:28:25PM +0000, Hunt, David wrote: --snip-- > > Hi Jan and Dave, > > I have reviewed your patches for arm[64] support. Please check the > review comments. Hi Jerin, I'm looking at the comments now, and working on getting the suggested changes merged into the patch-set. > Cavium would like to contribute on armv8 port and remaining libraries > (ACL, LPM, HASH) implementation for armv8. Currently i am re-basing > our ACL,HASH libraries implementation based on existing patches. > Happy to work with you guys to have full fledged armv8 support for DPDK. > > Jerin Thanks for that, it's good news indeed. > other query on rte_cpu_get_flag_enabled for armv8, > I have tried to run the existing patches on armv8-thunderX platform. > But there application start failure due to mismatch in > rte_cpu_get_flag_enabled() encoding. > > In my platform rte_cpu_get_flag_enabled() works based on > AT_HWCAP with following values[1] which different from > existing lib/librte_eal/common/include/arch/arm/rte_cpuflags.h > > [1]http://lxr.free-electrons.com/source/arch/arm64/include/uapi/asm/hwcap.h > > In order to debug this, Could provide the following > values in tested armv8 platform. Look like its running 32bit compatible > mode in your environment I'm using a Gigabyte MP30AR0 motherboard with an 8-core X-Gene, Running a 4.3.0-rc6 kernel. Here's the information on the cpu_flags issue you requested: > AT_SYSINFO_EHDR: 0x3ff859f0000 > AT_??? (0x26): 0x430f0a10 > AT_HWCAP: fb > AT_PAGESZ: 65536 > AT_CLKTCK: 100 > AT_PHDR: 0x400040 > AT_PHENT: 56 > AT_PHNUM: 7 > AT_BASE: 0x3ff85a00000 > AT_FLAGS: 0x0 > AT_ENTRY: 0x401900 > AT_UID: 0 > AT_EUID: 0 > AT_GID: 0 > AT_EGID: 0 > AT_SECURE: 0 > AT_RANDOM: 0x3ffef1c7988 > AT_EXECFN: /bin/sleep > AT_PLATFORM: aarch64 root@mp30ar0:~# LD_SHOW_AUXV=1 sleep 1000 AT_SYSINFO_EHDR: 0x7f7956d000 AT_HWCAP: 7 AT_PAGESZ: 4096 AT_CLKTCK: 100 AT_PHDR: 0x400040 AT_PHENT: 56 AT_PHNUM: 7 AT_BASE: 0x7f79543000 AT_FLAGS: 0x0 AT_ENTRY: 0x401900 AT_UID: 0 AT_EUID: 0 AT_GID: 0 AT_EGID: 0 AT_SECURE: 0 AT_RANDOM: 0x7ffcaf2e48 AT_EXECFN: /bin/sleep AT_PLATFORM: aarch64 > root@arm64:/export/dpdk-arm64# zcat /proc/config.gz | grep CONFIG_COMPAT > # CONFIG_COMPAT_BRK is not set > CONFIG_COMPAT_BINFMT_ELF=y > CONFIG_COMPAT=y > CONFIG_COMPAT_NETLINK_MESSAGES=y root@mp30ar0:~# zcat /proc/config.gz | grep CONFIG_COMPAT # CONFIG_COMPAT_BRK is not set CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_BINFMT_ELF=y CONFIG_COMPAT=y > root@arm64:/export/dpdk-arm64# cat /proc/cpuinfo > Processor : AArch64 Processor rev 0 (aarch64) > processor : 0 > processor : 1 --snip-- > processor : 46 > processor : 47 > Features : fp asimd aes pmull sha1 sha2 crc32 > CPU implementer : 0x43 > CPU architecture: AArch64 > CPU variant : 0x0 > CPU part : 0x0a1 > CPU revision : 0 root@mp30ar0:~# cat /proc/cpuinfo processor : 0 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 1 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 2 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 3 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 4 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 5 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 6 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 processor : 7 Features : fp asimd evtstrm CPU implementer : 0x50 CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 1 root@mp30ar0:~# Hope this helps. Regards, Dave.