From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id D5CD45A57 for ; Mon, 2 Nov 2015 16:21:01 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 02 Nov 2015 07:20:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,234,1444719600"; d="scan'208";a="809731357" Received: from dhunt5x-mobl3.ger.corp.intel.com (HELO [10.237.208.62]) ([10.237.208.62]) by orsmga001.jf.intel.com with ESMTP; 02 Nov 2015 07:20:44 -0800 To: Jan Viktorin References: <1446212826-19425-7-git-send-email-david.hunt@intel.com> <5633798B.2050708@intel.com> <20151030161106.4657232.16920.465@rehivetech.com> <56339AA9.1060505@intel.com> <20151102063209.GC17659@localhost.localdomain> <56373F59.6080602@intel.com> <20151102131710.GA10385@localhost.localdomain> <56377B6E.70502@intel.com> <20151102161318.66989bb9@pcviktorin.fit.vutbr.cz> From: "Hunt, David" Message-ID: <56377F4C.8020003@intel.com> Date: Mon, 2 Nov 2015 15:20:44 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151102161318.66989bb9@pcviktorin.fit.vutbr.cz> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v3 6/6] test: add checks for cpu flags on armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Nov 2015 15:21:02 -0000 On 02/11/2015 15:13, Jan Viktorin wrote: > On Mon, 2 Nov 2015 15:04:14 +0000 > "Hunt, David" wrote: > >> On 02/11/2015 13:17, Jerin Jacob wrote: >> -snip-- >>> If am not wrong existing rte_cpu_get_flag_enabled() implementation >>> should be broken in your platform also for arm64. as I could see only AT_HWCAP >>> not AT_HWCAP2 and AT_HWCAP is 0x7 that means your platform also >>> follows >>> >>> http://lxr.free-electrons.com/source/arch/arm64/include/uapi/asm/hwcap.h >>> >>> and the implmentation is >>> >>> FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0) // not correct for arm64 >>> FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1) // not correct for arm64 >>> FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2) // not correct for arm64 >>> FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3) >> --snip-- >>> FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4) >>> FEAT_DEF(AARCH32, 0x00000001, 0, REG_PLATFORM, 0) >>> FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1) >>> >>> Am I missing something ? >> >> You are correct. I need to re-visit this. In merging the ARMv7 and >> ARVv8, I should have split the hardware capabilities flags into 32-but >> and 64-bit versions. I'll do that in the next patch. >> Thanks, >> Dave. > > Should I split the rte_atomic.h and rte_cpuflags.h then? > > Jan It looks like we're headed in that direction, so yes, I think that would be a good idea. Dave