From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B72CEA0A0C; Wed, 4 Aug 2021 16:22:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3CCD841244; Wed, 4 Aug 2021 16:22:32 +0200 (CEST) Received: from out5-smtp.messagingengine.com (out5-smtp.messagingengine.com [66.111.4.29]) by mails.dpdk.org (Postfix) with ESMTP id B0B314123E for ; Wed, 4 Aug 2021 16:22:30 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 4DC275C00BE; Wed, 4 Aug 2021 10:22:30 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Wed, 04 Aug 2021 10:22:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm1; bh= wOFDhfvZy3Q/+xg031Nz2YKqE8uVYpswkf8QZkXtT7Q=; b=Lf/R718S/kVy+lnf Sh4IVEZXPIPk8g2oNB/ex+bSqG4X8ivpIv97UvwxAfr44HbiT2FbPQp87i0dT+Ni Cb4+25HUrP19pnSAWOPzzeoOFfhlqNXxV8r4dJBBpcfT7xavXTrugYc/jYaPq3XY WJJmR4RUakhxG7r8PVjqH+9goKnTaCYsJBahR6zXcOY1Vb0BO1y/ioKU4scMnVER j1q3pPliSTQZPq5WTl6szcJsBZAhUJpFvg+pGjkR6dIGw0UJk+Tj4avJd/bckV2k IYd/VJ54bdbmfieVs8+gVO63nPjOGWctE9LT/l4ynYMO+M13AEx3vA9KH3HXgZsh 3LZ1xQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=wOFDhfvZy3Q/+xg031Nz2YKqE8uVYpswkf8QZkXtT 7Q=; b=MnStI7/eWFglpczdYSRNMOrxtecYTPnaWqbBfxi53bRHcu2I4j8tIxK/P L0TS42LtseJ7Pp4XQOXlQoB3QP/qsYA5t34+JKr8SSLESrdWHV6u5gBqEQQKCqFm V3SR+BMJ7w8TJy0ir0JxaviwR53Ir+wyjw3/ISVBvt3u1JAXG/+Bb4dBgEjq9O9n tBWoYTRRlyPJcwV8tYs4CF8WEzVXfL1Gj26qk1mWa+bEmkxotQMCNIZpaYOxdu5L mvoApWBwz8R6oAO6y9KJveHq61MBVw1STQbKbGSTjpdseDGoLsd5uTc0LsJg7baT Ju5NuO3vu59PWx8ZLnL7EmBjadN6g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrieejgdehiecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenog fuuhhsphgvtghtffhomhgrihhnucdlgeelmdenucfjughrpefhvffufffkjghfggfgtges thfuredttddtvdenucfhrhhomhepvfhhohhmrghsucfoohhnjhgrlhhonhcuoehthhhomh grshesmhhonhhjrghlohhnrdhnvghtqeenucggtffrrghtthgvrhhnpeekfeehteektdev fefhheegvddtteeihefgffetgfdtgfdtteehudehgeehjeeiheenucffohhmrghinhepug hpughkrdhorhhgpdhgohhoghhlvgdrtghomhenucevlhhushhtvghrufhiiigvpedtnecu rfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 4 Aug 2021 10:22:28 -0400 (EDT) From: Thomas Monjalon To: Harman Kalra Cc: "Xia, Chenbo" , dev@dpdk.org, "jerinj@marvell.com" , "david.marchand@redhat.com" , Ray Kinsella , Jerin Jacob Date: Wed, 04 Aug 2021 16:22:26 +0200 Message-ID: <5694887.QAR4yK57Qd@thomas> In-Reply-To: References: <20210802160352.135754-1-hkalra@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] doc: announce: make rte intr handle internal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > Moving struct rte_intr_handle as an internal structure to > > > avoid any ABI breakages in future. Since this structure defines > > > some static arrays and changing respective macros breaks the ABI. > > > Eg: > > > Currently RTE_MAX_RXTX_INTR_VEC_ID imposes a limit of maximum 512 > > > MSI-X interrupts that can be defined for a PCI device, while PCI > > > specification allows maximum 2048 MSI-X interrupts that can be used. > > > If some PCI device requires more than 512 vectors, either change the > > > RTE_MAX_RXTX_INTR_VEC_ID limit or dynamically allocate based on > > > PCI device MSI-X size on probe time. Either way its an ABI breakage. > > > > > > Discussion thread: > > > https://mails.dpdk.org/archives/dev/2021-March/202959.html > > > > > > Change already included in 21.11 ABI improvement spreadsheet (item 42): > > > https://docs.google.com/spreadsheets/d/1betlC000ua5SsSiJIcC54mCCCJnW6voH5Dqv9U > > > xeyfE/edit#gid=0 > > > > > > Signed-off-by: Harman Kalra > > > --- > > > --- a/doc/guides/rel_notes/deprecation.rst > > > +++ b/doc/guides/rel_notes/deprecation.rst > > > +* eal: Making ``struct rte_intr_handle`` internal to avoid any ABI breakages > > > + in future. > > > + > > > > Acked-by: Chenbo Xia > > Acked-by: Jerin Jacob Acked-by: Andrew Rybchenko Applied, thanks.