From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6FF3A00E6 for ; Mon, 2 Sep 2019 05:01:11 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 87DB11C23A; Mon, 2 Sep 2019 05:01:11 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 959411C238 for ; Mon, 2 Sep 2019 05:01:09 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Sep 2019 20:01:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,457,1559545200"; d="scan'208";a="183204601" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga007.fm.intel.com with ESMTP; 01 Sep 2019 20:01:08 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 1 Sep 2019 20:01:08 -0700 Received: from fmsmsx604.amr.corp.intel.com (10.18.126.84) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Sun, 1 Sep 2019 20:01:05 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx604.amr.corp.intel.com (10.18.126.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Sun, 1 Sep 2019 20:01:05 -0700 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.23]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.86]) with mapi id 14.03.0439.000; Mon, 2 Sep 2019 11:01:04 +0800 From: "Pei, Andy" To: "Ye, Xiaolong" CC: "dev@dpdk.org" , "Xu, Rosen" , "Zhang, Tianfei" Thread-Topic: [dpdk-dev] [PATCH v2] net/ipn3ke: setup MTU when HW init Thread-Index: AQHVV+gcjhPJGPV3lU2CR14bqR3cnqcXttGA Date: Mon, 2 Sep 2019 03:01:03 +0000 Message-ID: <5941F446C088714A85408FA3132CFCBB0106B6E2@SHSMSX105.ccr.corp.intel.com> References: <1565255540-308917-1-git-send-email-andy.pei@intel.com> <1565280090-344032-1-git-send-email-andy.pei@intel.com> <20190821061548.GA87622@intel.com> In-Reply-To: <20190821061548.GA87622@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/ipn3ke: setup MTU when HW init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" HI xiaolong, Reply inline. -----Original Message----- From: Ye, Xiaolong=20 Sent: Wednesday, August 21, 2019 2:16 PM To: Pei, Andy Cc: dev@dpdk.org; Xu, Rosen ; Zhang, Tianfei Subject: Re: [dpdk-dev] [PATCH v2] net/ipn3ke: setup MTU when HW init On 08/09, Andy Pei wrote: >set up mtu to the minimun in tx mtu, rx mtu and IPN3KE_MAC_FRAME_SIZE_MAX. > >Signed-off-by: Andy Pei >--- >v2: >* modify low bound and upper bound. > > drivers/net/ipn3ke/ipn3ke_ethdev.c | 97=20 > ++++++++++++++++++++++++++++++++++++++ > drivers/net/ipn3ke/ipn3ke_ethdev.h | 19 ++++++++ > 2 files changed, 116 insertions(+) > >diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c=20 >b/drivers/net/ipn3ke/ipn3ke_ethdev.c >index c226d63..1a6c217 100644 >--- a/drivers/net/ipn3ke/ipn3ke_ethdev.c >+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c >@@ -209,6 +209,100 @@ > return 0; > } >=20 >+static void ipn3ke_10G_mtu_setup >+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) The dpdk convention is: static void ipn3ke_10G_mtu_setup(xxx) OK >+{ >+ uint32_t tx; >+ uint32_t rx; >+ uint32_t tmp; >+ >+ (*hw->f_mac_read)(hw, >+ &tx, >+ IPN3KE_10G_TX_FRAME_MAXLENGTH, >+ mac_num, >+ eth_group_sel); Need to verify whether hw->f_mac_read is NULL or not. ok >+ >+ (*hw->f_mac_read)(hw, >+ &rx, >+ IPN3KE_10G_RX_FRAME_MAXLENGTH, >+ mac_num, >+ eth_group_sel); >+ >+ tmp =3D (tx > rx) ? rx : tx; Can use RTE_MIN OK >+ if (tmp < RTE_ETHER_MIN_MTU) >+ tmp =3D RTE_ETHER_MIN_MTU; >+ if (tmp > IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD) >+ tmp =3D IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD; >+ >+ (*hw->f_mac_write)(hw, >+ tmp, >+ IPN3KE_10G_TX_FRAME_MAXLENGTH, >+ mac_num, >+ eth_group_sel); >+ >+ (*hw->f_mac_write)(hw, >+ tmp, >+ IPN3KE_10G_RX_FRAME_MAXLENGTH, >+ mac_num, >+ eth_group_sel); Need to check f_mac_write is not NULL before calling it. ok >+} >+ >+static void ipn3ke_25G_mtu_setup >+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) { >+ uint32_t tx; >+ uint32_t rx; >+ uint32_t tmp; >+ >+ (*hw->f_mac_read)(hw, >+ &tx, >+ IPN3KE_25G_MAX_TX_SIZE_CONFIG, >+ mac_num, >+ eth_group_sel); >+ >+ (*hw->f_mac_read)(hw, >+ &rx, >+ IPN3KE_25G_MAX_RX_SIZE_CONFIG, >+ mac_num, >+ eth_group_sel); >+ >+ tmp =3D (tx > rx) ? rx : tx; >+ if (tmp < RTE_ETHER_MIN_MTU) >+ tmp =3D RTE_ETHER_MIN_MTU; >+ if (tmp > IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD) >+ tmp =3D IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD; >+ >+ (*hw->f_mac_write)(hw, >+ tmp, >+ IPN3KE_25G_MAX_TX_SIZE_CONFIG, >+ mac_num, >+ eth_group_sel); >+ >+ (*hw->f_mac_write)(hw, >+ tmp, >+ IPN3KE_25G_MAX_RX_SIZE_CONFIG, >+ mac_num, >+ eth_group_sel); >+} >+ ipn3ke_10G_mtu_setup and ipn3ke_25G_mtu_setup share most of the code, pleas= e try to refactor to avoid duplicate code. ok >+static void >+ipn3ke_mtu_setup(struct ipn3ke_hw *hw) { >+ int i; >+ if (hw->retimer.mac_type =3D=3D IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) = { >+ for (i =3D 0; i < hw->port_num; i++) { >+ ipn3ke_10G_mtu_setup(hw, i, 0); >+ ipn3ke_10G_mtu_setup(hw, i, 1); >+ } >+ } else if (hw->retimer.mac_type =3D=3D >+ IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { >+ for (i =3D 0; i < hw->port_num; i++) { >+ ipn3ke_25G_mtu_setup(hw, i, 0); >+ ipn3ke_25G_mtu_setup(hw, i, 1); >+ } >+ } >+} >+ > static int > ipn3ke_hw_init(struct rte_afu_device *afu_dev, > struct ipn3ke_hw *hw) >@@ -303,6 +397,9 @@ > } > } >=20 >+ /* init mtu */ >+ ipn3ke_mtu_setup(hw); >+ > ret =3D rte_eth_switch_domain_alloc(&hw->switch_domain_id); > if (ret) > IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device=20 >%d", diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h=20 >b/drivers/net/ipn3ke/ipn3ke_ethdev.h >index c7b336b..6419da3 100644 >--- a/drivers/net/ipn3ke/ipn3ke_ethdev.h >+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h >@@ -654,6 +654,25 @@ static inline void _ipn3ke_indrct_write(struct=20 >ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ > IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) >=20 >+/* Additional Feature Register */ >+#define ADD_PHY_CTRL 0x0 >+#define PHY_RESET BIT(0) >+/* registers for 25G/40G mac */ >+#define MAC_CONFIG 0x310 >+#define MAC_RESET_MASK GENMASK(2, 0) >+ >+#define IPN3KE_MAX_MTU 0xff= ff >+ >+#define IPN3KE_25G_PHY_PMA_SLOOP 0x31= 3 >+#define IPN3KE_25G_TX_FLOW_CTRL 0x64= 0 >+#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x40= 7 >+#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x50= 6 >+ >+#define IPN3KE_10G_TX_PAUSE_FRAME_QUANTA 0x00= 42 >+#define IPN3KE_10G_TX_PAUSE_FRAME_HOLDOFF 0x00= 43 >+#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x00= 2C >+#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0x00= AE >+ > #define IPN3KE_REGISTER_WIDTH 32 I saw some MACRO definitions are not used in this patch. I copy these MACRO from ipn3ke kernel driver in case we will use later. If not use currently, I can delete these MACRO. And by the way, why there is no mtu_set ops for ipn3ke ethdev? Mtu_set ops is in ipn3ke_representor.c Thanks, Xiaolong >=20 > /*Bits[2:0]: Configuration of TX statistics counters: >-- >1.8.3.1 >