From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 47FCFA00BE; Thu, 31 Oct 2019 03:39:51 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 100511C11F; Thu, 31 Oct 2019 03:39:51 +0100 (CET) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id E51301C11B for ; Thu, 31 Oct 2019 03:39:48 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 19:39:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,249,1569308400"; d="scan'208";a="230687260" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga002.fm.intel.com with ESMTP; 30 Oct 2019 19:39:47 -0700 Received: from fmsmsx607.amr.corp.intel.com (10.18.126.87) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 30 Oct 2019 19:39:47 -0700 Received: from fmsmsx607.amr.corp.intel.com (10.18.126.87) by fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 30 Oct 2019 19:39:46 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 30 Oct 2019 19:39:46 -0700 Received: from shsmsx105.ccr.corp.intel.com ([169.254.11.225]) by shsmsx102.ccr.corp.intel.com ([169.254.2.108]) with mapi id 14.03.0439.000; Thu, 31 Oct 2019 10:39:45 +0800 From: "Pei, Andy" To: "Ye, Xiaolong" CC: "dev@dpdk.org" , "Xu, Rosen" , "Zhang, Tianfei" , "Yigit, Ferruh" Thread-Topic: [PATCH v14 00/19] add PCIe AER disable and IRQ support for ipn3ke Thread-Index: AQHVj4+ov4Dg1QphyEWlM/hGkDm25Kd0CblA Date: Thu, 31 Oct 2019 02:39:44 +0000 Message-ID: <5941F446C088714A85408FA3132CFCBB010A2515@SHSMSX105.ccr.corp.intel.com> References: <1571917119-149534-2-git-send-email-andy.pei@intel.com> <1572252623-96127-1-git-send-email-andy.pei@intel.com> <20191031020129.GJ11315@intel.com> In-Reply-To: <20191031020129.GJ11315@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v14 00/19] add PCIe AER disable and IRQ support for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Thanks Xiaolong. -----Original Message----- From: Ye, Xiaolong=20 Sent: Thursday, October 31, 2019 10:01 AM To: Pei, Andy Cc: dev@dpdk.org; Xu, Rosen ; Zhang, Tianfei ; Yigit, Ferruh Subject: Re: [PATCH v14 00/19] add PCIe AER disable and IRQ support for ipn= 3ke On 10/28, Andy Pei wrote: >This patch set adds PCIe AER disable and FPGA interrupt support for=20 >ipn3ke. It also provides a small rework for port bonding between FPGA=20 >line side port and I40e PF port. > >What is the PCI Express AER(Advanced Error Reporting)? >Advanced Error Reporting capability is implemented with a PCI Express=20 >advanced error reporting extended capability structure providing more=20 >robust error reporting. It's also one of PCI Express error reporting=20 >paradigms. AER is supported by most of PCIe devices. > >In PAC N3000 card, some uncertainty errors will cause FPGA reload, such=20 >as temperature is higher than threshold. From Software point of view,=20 >FPGA reload means FPGA unplug and plug. For avoiding system crash we=20 >need to clear AER register before these errors occur. > >Currently PAC N3000 card FME and AFU all provide interrupts, in ifpga=20 >rawdev driver, we implement a FME interrupt function to notify errors=20 >reported by FME. Besides this, OPAE share code also provide a common=20 >AFU interrupt API for users to register their own interrupt functions. > Series applied to dpdk-next-net-intel. Thanks.