From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 26CB458D7 for ; Thu, 28 Nov 2013 12:00:44 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 28 Nov 2013 03:01:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.93,790,1378882800"; d="scan'208";a="435596291" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga001.fm.intel.com with ESMTP; 28 Nov 2013 03:01:43 -0800 Received: from irsmsx152.ger.corp.intel.com (163.33.192.66) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.123.3; Thu, 28 Nov 2013 11:01:41 +0000 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.66]) by IRSMSX152.ger.corp.intel.com ([169.254.6.169]) with mapi id 14.03.0123.003; Thu, 28 Nov 2013 11:01:41 +0000 From: "Richardson, Bruce" To: Thomas Monjalon , Dmitry Vyal Thread-Topic: [dpdk-dev] Sporadic errors while initializing NICs in example applications, dpdk-1.5.0r1 Thread-Index: AQHO637zf5Sm98fTc0e2aLigBY+K5Jo6ec4A Date: Thu, 28 Nov 2013 11:01:41 +0000 Message-ID: <59AF69C657FD0841A61C55336867B5B01A9781FC@IRSMSX103.ger.corp.intel.com> References: <528F4E41.2000405@gmail.com> <201311221348.02307.thomas.monjalon@6wind.com> <5295FC76.70201@gmail.com> <201311271542.05288.thomas.monjalon@6wind.com> In-Reply-To: <201311271542.05288.thomas.monjalon@6wind.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] Sporadic errors while initializing NICs in example applications, dpdk-1.5.0r1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Nov 2013 11:00:46 -0000 >=20 > It's probably due to a frequency scaling. > The timer based is initialized when DPDK initialize and the CPU can chang= e > its frequency, breaking next timers. >=20 > The fix is to control the CPU frequency. > Please try this, without your patch: > for g in /sys/devices/system/cpu/*/cpufreq/scaling_governor; do > echo performance >$g; done The right fix for applications (examples and > testpmd included) could be to call rte_power_init(). Patches are welcomed= . >=20 [BR] Frequency changes should not affect timers for modern Intel CPUs. Plea= se see the " Intel(r) 64 and IA-32 Architectures Software Developer's Manua= l" Volume 3 (http://www.intel.com/content/dam/www/public/us/en/documents/ma= nuals/64-ia-32-architectures-software-developer-system-programming-manual-3= 25384.pdf) , Section 17.13 for more details on this.=20