From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 1DCFA8E7B for ; Tue, 3 Nov 2015 18:02:37 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 03 Nov 2015 09:02:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,239,1444719600"; d="scan'208";a="841666335" Received: from irsmsx154.ger.corp.intel.com ([163.33.192.96]) by orsmga002.jf.intel.com with ESMTP; 03 Nov 2015 09:02:36 -0800 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.116]) by IRSMSX154.ger.corp.intel.com ([169.254.12.252]) with mapi id 14.03.0248.002; Tue, 3 Nov 2015 17:02:35 +0000 From: "Richardson, Bruce" To: Jerin Jacob , "Ananyev, Konstantin" Thread-Topic: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter Thread-Index: AQHRFlNtvkfUftDDJESs/4mJqnavcJ6KfI4AgAAHFYCAAAJLcA== Date: Tue, 3 Nov 2015 17:02:34 +0000 Message-ID: <59AF69C657FD0841A61C55336867B5B035967AC4@IRSMSX103.ger.corp.intel.com> References: <1446565921-18088-1-git-send-email-jerin.jacob@caviumnetworks.com> <2601191342CEEE43887BDE71AB97725836AB8F01@irsmsx105.ger.corp.intel.com> <20151103161834.GA18450@localhost.localdomain> <2601191342CEEE43887BDE71AB97725836AB8F55@irsmsx105.ger.corp.intel.com> <20151103165318.GA19474@localhost.localdomain> In-Reply-To: <20151103165318.GA19474@localhost.localdomain> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Nov 2015 17:02:38 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > Sent: Tuesday, November 3, 2015 4:53 PM > To: Ananyev, Konstantin > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter >=20 > On Tue, Nov 03, 2015 at 04:28:00PM +0000, Ananyev, Konstantin wrote: > > > > > > > -----Original Message----- > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > Sent: Tuesday, November 03, 2015 4:19 PM > > > To: Ananyev, Konstantin > > > Cc: dev@dpdk.org > > > Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > On Tue, Nov 03, 2015 at 03:57:24PM +0000, Ananyev, Konstantin wrote: > > > > > > > > > > > > > -----Original Message----- > > > > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > > > > > Sent: Tuesday, November 03, 2015 3:52 PM > > > > > To: dev@dpdk.org > > > > > Subject: [dpdk-dev] [RFC ][PATCH] Introduce > > > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter > > > > > > > > > > rte_ring implementation needs explicit memory barrier in weakly > > > > > ordered architecture like ARM unlike strongly ordered > > > > > architecture like X86 > > > > > > > > > > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration to > > > > > abstract such dependency so that other weakly ordered > > > > > architectures can reuse this infrastructure. > > > > > > > > Looks a bit clumsy. > > > > Please try to follow this suggestion instead: > > > > http://dpdk.org/ml/archives/dev/2015-October/025505.html > > > > > > Make sense. Do we agree on a macro that is defined based upon > > > RTE_ARCH_STRONGLY_ORDERED_MEM_OP to remove clumsy #ifdef every where = ? > > > > Why do we need that macro at all? > > Why just not have architecture specific macro as was discussed in that > thread? > > > > So for intel somewhere inside > > lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > it would be: > > > > #define rte_smp_wmb() rte_compiler_barrier() > > > > For arm inside lib/librte_eal/common/include/arch/x86/rte_atomic.h > > > > #define rte_smp_wmb() rte_wmb() >=20 > I am not sure about the other architecture but in armv8 device memory > (typically mapped through NIC PCIe BAR space) are strongly ordered. > So there is one more dimension to the equation(normal memory or device > memory). > IMO rte_smp_wmb() -> rte_wmb() mapping to deal with device memory may not > be correct on arm64 ? >=20 > Thoughts ? >=20 In cases like that I don't think barriers are needed on any platform so the= proposed scheme will work fine. It's up the driver writer to know about wh= en they are writing to device BARs or not. /Bruce