From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <bruce.richardson@intel.com> Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 38AEB1BD84 for <dev@dpdk.org>; Wed, 4 Apr 2018 12:38:32 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Apr 2018 03:38:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,405,1517904000"; d="scan'208";a="217535230" Received: from irsmsx109.ger.corp.intel.com ([163.33.3.23]) by fmsmga005.fm.intel.com with ESMTP; 04 Apr 2018 03:38:30 -0700 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.61]) by IRSMSX109.ger.corp.intel.com ([169.254.13.170]) with mapi id 14.03.0319.002; Wed, 4 Apr 2018 11:38:29 +0100 From: "Richardson, Bruce" <bruce.richardson@intel.com> To: Shreyansh Jain <shreyansh.jain@nxp.com>, "Xu, Rosen" <rosen.xu@intel.com>, "dev@dpdk.org" <dev@dpdk.org> CC: "Doherty, Declan" <declan.doherty@intel.com>, "Yigit, Ferruh" <ferruh.yigit@intel.com>, "Ananyev, Konstantin" <konstantin.ananyev@intel.com>, "Zhang, Tianfei" <tianfei.zhang@intel.com>, "Wu, Hao" <hao.wu@intel.com>, "gaetan.rivet@6wind.com" <gaetan.rivet@6wind.com> Thread-Topic: [PATCH v5 0/3] Introduce Intel FPGA BUS Thread-Index: AQHTy+EOOOt/r8lxG0iSgPKwJIw/xqPwUuEAgAAW+TA= Date: Wed, 4 Apr 2018 10:38:28 +0000 Message-ID: <59AF69C657FD0841A61C55336867B5B07227141A@IRSMSX103.ger.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522824677-86958-1-git-send-email-rosen.xu@intel.com> <HE1PR0402MB2780CC1B634FEA2CA05A8E3890A40@HE1PR0402MB2780.eurprd04.prod.outlook.com> In-Reply-To: <HE1PR0402MB2780CC1B634FEA2CA05A8E3890A40@HE1PR0402MB2780.eurprd04.prod.outlook.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjMxM2NmOWQtZTc2Mi00Njc5LWI3N2QtYzg0YTRiMTkxYzQ5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ4RGsyK2lSd1ZSQ2N5Y09LdFFyTGxuYXQxWGgzXC9xQkUyOTRBU0VMc2lrRjBzRHBSd0tYVG5yb05XRkE1K1FMRiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Wed, 04 Apr 2018 10:38:32 -0000 > -----Original Message----- > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > Sent: Wednesday, April 4, 2018 11:14 AM > To: Xu, Rosen <rosen.xu@intel.com>; dev@dpdk.org > Cc: Doherty, Declan <declan.doherty@intel.com>; Richardson, Bruce > <bruce.richardson@intel.com>; Yigit, Ferruh <ferruh.yigit@intel.com>; > Ananyev, Konstantin <konstantin.ananyev@intel.com>; Zhang, Tianfei > <tianfei.zhang@intel.com>; Wu, Hao <hao.wu@intel.com>; > gaetan.rivet@6wind.com > Subject: RE: [PATCH v5 0/3] Introduce Intel FPGA BUS >=20 > Hello Rosen, >=20 > > -----Original Message----- > > From: Rosen Xu [mailto:rosen.xu@intel.com] > > Sent: Wednesday, April 4, 2018 12:21 PM > > To: dev@dpdk.org > > Cc: declan.doherty@intel.com; bruce.richardson@intel.com; Shreyansh > > Jain <shreyansh.jain@nxp.com>; ferruh.yigit@intel.com; > > konstantin.ananyev@intel.com; tianfei.zhang@intel.com; > > hao.wu@intel.com; gaetan.rivet@6wind.com > > Subject: [PATCH v5 0/3] Introduce Intel FPGA BUS > > > > Intel FPGA BUS in DPDK > > ------------------------- > > > > This patch set introduces Intel FPGA BUS support in DPDK. > > > > v5 updates: > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > - Fixed SHARED LIB Build issue > > - Changed command name to IFPGA Rawdev name, > > so remove pci library datastruct and function. > > - Fixed PATCH v2/v3/v4 comments > > >=20 > [...] >=20 > Primary problems I see with your patches: > 1. They are not split enough. Still the patch 2/3 is dependent on 3/3. > That mean, it would break the compilation. There is no simpler way to > solve this except breaking the patch into multiple patches and slowly > introducing each function/feature. > (One obvious way would be to have 3/3 as 2/3 and vice-versa - Not sure > what that blocks). >=20 > 2. Documentation - there is none right now. Being a special use case for > PCI, I think a lot of people would benefit if you can explain the comment= s > about why iFPGA bus is required through documentation. >=20 > 3. Meson as requested by Bruce. Problem you will face is that rawdev > doesn't yet have meson enabled. I will work on that. If you can still > rework your patches for (1)+(2), I think meson enable over rawdev would b= e > trivial. I just spotted this and I've sent a patch for rawdev. It was pretty trivial= . :-) Please review and ack if you have the chance. The skeleton rawdev however, = I haven't done, so feel free to patch in that. /Bruce