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[62.23.145.78]) by smtp.gmail.com with ESMTPSA id i2sm4243555wmo.40.2021.06.17.04.24.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Jun 2021 04:24:54 -0700 (PDT) To: Ruifeng Wang , "dev@dpdk.org" Cc: "thomas@monjalon.net" , "jerinj@marvell.com" , Honnappa Nagarahalli , =?UTF-8?Q?Juraj_Linke=c5=a1?= , nd References: <20210525082402.8051-1-thierry.herbelot@6wind.com> <876d348bb6ab493f404c2c1f288262ff3112cada.1623917721.git.thierry.herbelot@6wind.com> From: Thierry Herbelot Message-ID: <60bf1e0d-5b39-1f7f-c75b-c2d4b0b45107@6wind.com> Date: Thu, 17 Jun 2021 13:24:54 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH V3] config/arm: add Qualcomm Centriq 2400 part number X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 6/17/21 12:03 PM, Ruifeng Wang wrote: >> -----Original Message----- >> From: Thierry Herbelot >> Sent: Thursday, June 17, 2021 4:16 PM >> To: dev@dpdk.org >> Cc: Thierry Herbelot ; thomas@monjalon.net; >> jerinj@marvell.com; Ruifeng Wang ; Honnappa >> Nagarahalli ; Juraj Linkeš >> >> Subject: [PATCH V3] config/arm: add Qualcomm Centriq 2400 part number >> >> 0xc00 is for "SoC 2.0" Qualcomm Centriq servers. >> 0x800 is for "SoC 1.1". >> >> Cc: Jerin Jacob >> Cc: Ruifeng Wang >> Cc: Honnappa Nagarahalli >> Cc: Juraj Linkeš >> >> Signed-off-by: Thierry Herbelot >> -- >> V2: add maintainers as Cc >> V3: fix meson syntax for the SoC v1.1 machine description >> --- >> config/arm/meson.build | 12 ++++++++++-- >> 1 file changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index >> e83a56e0d589..b33303d09023 100644 >> --- a/config/arm/meson.build >> +++ b/config/arm/meson.build >> @@ -179,7 +179,8 @@ implementer_qualcomm = { >> ['RTE_MAX_NUMA_NODES', 1] >> ], >> 'part_number_config': { >> - '0xc00': {'machine_args': ['-march=armv8-a+crc']} >> + '0x800': {'machine_args': ['-march=armv8-a+crc']}, >> + '0xc00': {'machine_args': ['-march=armv8-a+crc']}, >> } >> } >> >> @@ -223,8 +224,15 @@ soc_bluefield = { >> 'numa': false >> } >> >> +soc_centriq2400_v1_1 = { >> + 'description': 'Qualcomm Centriq 2400 (SoC v1.1)', >> + 'implementer': '0x51', >> + 'part_number': '0x800', >> + 'numa': false >> +} >> + > What is the difference between SoC v1.1 and SoC v2.0. Do they have different instruction levels or extensions? > They have the same machine_args. I think the two part numbers can share the same soc_xx. Because cross built binary can run on both SoCs. > What do you think? Hello, There is no visible differences between the two versions. How do we merge the soc_centriq2400 configurations ? It would seem it is only possible to have one part_number per soc configuration. Thierry > > Thanks. >> soc_centriq2400 = { >> - 'description': 'Qualcomm Centriq 2400', >> + 'description': 'Qualcomm Centriq 2400 (SoC v2.0)', >> 'implementer': '0x51', >> 'part_number': '0xc00', >> 'numa': false >> -- >> 2.29.2 > -- Thierry Herbelot Senior Software Engineer Tel: +33 1 39 30 92 61 http://www.6wind.com/ Follow us: https://www.linkedin.com/company/6wind/ https://twitter.com/6WINDsoftware https://www.youtube.com/user/6windsoftware