From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CC95A0C4B; Fri, 8 Oct 2021 22:16:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 85C8940DDA; Fri, 8 Oct 2021 22:16:47 +0200 (CEST) Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by mails.dpdk.org (Postfix) with ESMTP id 3EC34407FF for ; Fri, 8 Oct 2021 22:16:46 +0200 (CEST) Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 9D0165C017D; Fri, 8 Oct 2021 16:16:45 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute6.internal (MEProxy); Fri, 08 Oct 2021 16:16:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= zT4gLRlqu3kt03ZHonu3IH4bcvWfeo+6P3Rw9oVZbOQ=; b=hYn49z505sv3UoK8 3SkGNA0SPE3SrScHapPDrqlqlqaT5w6VlMRTO92KcEckW3n8NubtVGHylRkH9CQl /W5gvVJEUOuP17Th3aHlgqYIvSY7A/Rb2dA9nuePAr6VzVYwU26y0W0LZnqyktaO f16Db9NAHdz8QucZHUoESAklygV5EExMVtzmXJ6LaM8s5a/AKPBGFELs6QFnaAVx QEs70Tu4GIsx1xknAm5IdCvpz7DgqAxmrku5uBiYmOSx+XdqigAFy9lGmSLDgx6/ r7q3/6QbH13wurS+zf1fvsheTBZh6bI6qMY6jdEc4kQXrjllQzQgzznQzhZReuaE akMIng== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=zT4gLRlqu3kt03ZHonu3IH4bcvWfeo+6P3Rw9oVZb OQ=; b=btIAu7u/YAmpuMq97gxb57/Cwl3hxpfFUYE+qV1LZrFCwPvOqwZ9egN1j Eu6O78URiIepRJCxzzpjQah12zObcITj0mrVqFHxMrDQuJa5HOjV3RYuiSoaDTrG cSVE9gckpXbEZRqZP7Tq66OyG58ZEme7c/qmpkYTA3U0SULCub1soA++0HW8RZ1n vgAV0+nLm7Rzk/dXKaZ8qk/j9NIwMHhlZ7NYrB19t+KqRYMZEMfzxhkH3U3gc8ij DlmcHzjZi2+gqLWGUBR96uX2Sqmwfncg0PSGFuOFIjvwTv5Qc2ZWHouTAgUBHuLz D7X37GZ8qjEGCybW7I2IB6IwLINJw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrvddttddgudeggecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhm rghsucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenuc ggtffrrghtthgvrhhnpedugefgvdefudfftdefgeelgffhueekgfffhfeujedtteeutdej ueeiiedvffegheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 8 Oct 2021 16:16:44 -0400 (EDT) From: Thomas Monjalon To: Elena Agostini Cc: dev@dpdk.org Date: Fri, 08 Oct 2021 22:16:41 +0200 Message-ID: <6121049.9gYzhInuAM@thomas> In-Reply-To: <20211009015349.9694-7-eagostini@nvidia.com> References: <20210602203531.2288645-1-thomas@monjalon.net> <20211009015349.9694-1-eagostini@nvidia.com> <20211009015349.9694-7-eagostini@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v3 6/9] gpudev: add memory barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 09/10/2021 03:53, eagostini@nvidia.com: > From: Elena Agostini > > Add a function for the application to ensure the coherency > of the writes executed by another device into the GPU memory. > > Signed-off-by: Elena Agostini > --- > +/** > + * @warning > + * @b EXPERIMENTAL: this API may change without prior notice. > + * > + * Enforce a GPU memory write barrier. > + * > + * @param dev_id > + * Reference device ID. > + * > + * @return > + * 0 on success, -rte_errno otherwise: > + * - ENODEV if invalid dev_id > + * - ENOTSUP if operation not supported by the driver > + * - EPERM if driver error > + */ > +__rte_experimental > +int rte_gpu_mbw(int16_t dev_id); I would replace mbw with wmb. Also it may be worth adding few more words about the goal: ensure that previous writes in GPU memory are complete? Does it work for writes done from CPU? from GPU?