From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AF6F4404F; Wed, 12 Jun 2024 17:27:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C3EE443353; Wed, 12 Jun 2024 17:07:28 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mails.dpdk.org (Postfix) with ESMTP id 174C742FCF for ; Wed, 12 Jun 2024 17:07:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718204838; x=1749740838; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9zeSjtjB+s7y20kjNigMyOxKywRKYqCZr5gUZ4tu3sM=; b=XPDQMTkjxUelM92YX7ZzwM3g/cc+6XEwQfCHXWyh2F4OXqWcyFX8bPg6 f5fV3BZQB1CrOL48Ubx1C1PJhOF74EI0UgX8PKI1lTsS+7+YeNul+IxXq St1wELy2ny1mRKdDNF0N0UTyvFznmu+NvO7xgWiQzetTVYqN3Cxa2c3FH pjt4VIlNgYWObegge2J47u3Mt6lAhYj5DofqGIBcLpe9zPyScBxTkm4G1 3HTgWVL6tLxTw55onD8ltPcXyymMW0Zc8cCIxZ0+zAFDPR5hqncfTKQnG 6c2KwFcenP4HvyVrDZQknLUselJhSCdb1VA++ZHse69sLB2oQnjZCmHSP A==; X-CSE-ConnectionGUID: lL67tTUVSZSK15bHlj7bAQ== X-CSE-MsgGUID: 1ygXUZYpQDGxKJmDkw7G5w== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="32460177" X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="32460177" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2024 08:07:18 -0700 X-CSE-ConnectionGUID: lDP0OJcCTVSKyMvVJKuhmQ== X-CSE-MsgGUID: rRQR4rEWSqiQhxByRATo2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="39926103" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 12 Jun 2024 08:07:17 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Ian Stokes , bruce.richardson@intel.com, Jacob Keller Subject: [PATCH v2 144/148] net/ice/base: rename SMA register macros to match Linux upstream Date: Wed, 12 Jun 2024 16:02:18 +0100 Message-ID: <622518a59fc4a70a156b87f900b2774af02f6beb.1718204529.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20240430154014.1026-1-ian.stokes@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ian Stokes The macros used to define the bits for controlling the SMA are different to what we published upstream. We don't have a strong justification to change the upstream names, so fix the out-of-tree shared code to use the names as published upstream. Signed-off-by: Jacob Keller Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.h | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 345d343a5a..9357dfd327 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -646,6 +646,21 @@ ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) #define E830_HIGH_TX_MEMORY_BANK(slot, port) \ (E830_PRTTSYN_TXTIME_H(slot) + 0x8 * (port)) +/* E810T SMA controller pin control */ +#define ICE_SMA1_DIR_EN_E810T BIT(4) +#define ICE_SMA1_TX_EN_E810T BIT(5) +#define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3) +#define ICE_SMA2_DIR_EN_E810T BIT(6) +#define ICE_SMA2_TX_EN_E810T BIT(7) + +#define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \ + ICE_SMA1_TX_EN_E810T) +#define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \ + ICE_SMA2_DIR_EN_E810T | \ + ICE_SMA2_TX_EN_E810T) +#define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \ + ICE_SMA2_MASK_E810T) + #define ICE_SMA_MIN_BIT_E810T 3 #define ICE_SMA_MAX_BIT_E810T 7 #define ICE_PCA9575_P1_OFFSET 8 @@ -660,11 +675,6 @@ ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) /* E810T PCA9575 IO controller pin control */ #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4) -#define ICE_E810T_P1_SMA1_DIR_EN BIT(4) -#define ICE_E810T_P1_SMA1_TX_EN BIT(5) -#define ICE_E810T_P1_SMA2_UFL2_RX_DIS BIT(3) -#define ICE_E810T_P1_SMA2_DIR_EN BIT(6) -#define ICE_E810T_P1_SMA2_TX_EN BIT(7) /* 56G PHY quad register base addresses */ #define ICE_PHY0_BASE 0x092000 -- 2.43.0